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clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic()

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Use readl_poll_timeout_atomic() instead of open-coding the same
operation.

As typically no retries are needed, 10 µs is a suitable timeout value.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/900543d4b9abc1004e6aecdb676f23e5508ae96f.1685692810.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2023-06-02 10:50:40 +02:00
parent d0414e762f
commit 7df8eea64a
1 changed files with 5 additions and 11 deletions
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16
drivers/clk/renesas/rzg2l-cpg.c
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@ -903,9 +903,9 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
unsigned int reg = clock->off;
struct device *dev = priv->dev;
unsigned long flags;
unsigned int i;
u32 bitmask = BIT(clock->bit);
u32 value;
int error;
if (!clock->off) {
dev_dbg(dev, "%pC does not support ON/OFF\n", hw->clk);
@ -930,19 +930,13 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
if (!priv->info->has_clk_mon_regs)
return 0;
for (i = 1000; i > 0; --i) {
if (((readl(priv->base + CLK_MON_R(reg))) & bitmask))
break;
cpu_relax();
}
if (!i) {
error = readl_poll_timeout_atomic(priv->base + CLK_MON_R(reg), value,
value & bitmask, 0, 10);
if (error)
dev_err(dev, "Failed to enable CLK_ON %p\n",
priv->base + CLK_ON_R(reg));
return -ETIMEDOUT;
}
return 0;
return error;
}
static int rzg2l_mod_clock_enable(struct clk_hw *hw)