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drm/i915: Implement stolen reserved detection for ctg/elk
Finally managed to dig up enough hints as to where the stolen reserved stuff lives on ctg/elk. So add the code to decode it. This was a combination of old chipset specs, diggin up an old elk grits release with an ctg/elk AubLoad etc. This was only tested on an elk as I don't have a ctg here unfortunately. This leaves ilk as the only platform that doesn't have a way to detect this stuff. Looking at the register contents on my ilk, it might be that the elk way works there too, but I can't be sure since I can't affect the amount of reserved memory on that machine, and if I am to trust the register contents, by default it would reserve 0 bytes. v2: s/WARN_ON_ONCE/WARN_ON/ since it's in one time init code anyway (Paulo) Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -196,6 +196,29 @@ void i915_gem_cleanup_stolen(struct drm_device *dev)
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drm_mm_takedown(&dev_priv->mm.stolen);
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}
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static void g4x_get_stolen_reserved(struct drm_i915_private *dev_priv,
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unsigned long *base, unsigned long *size)
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{
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uint32_t reg_val = I915_READ(IS_GM45(dev_priv) ?
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CTG_STOLEN_RESERVED :
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ELK_STOLEN_RESERVED);
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unsigned long stolen_top = dev_priv->mm.stolen_base +
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dev_priv->gtt.stolen_size;
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*base = (reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK) << 16;
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WARN_ON((reg_val & G4X_STOLEN_RESERVED_ADDR1_MASK) < *base);
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/* On these platforms, the register doesn't have a size field, so the
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* size is the distance between the base and the top of the stolen
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* memory. We also have the genuine case where base is zero and there's
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* nothing reserved. */
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if (*base == 0)
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*size = 0;
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else
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*size = stolen_top - *base;
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}
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static void gen6_get_stolen_reserved(struct drm_i915_private *dev_priv,
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unsigned long *base, unsigned long *size)
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{
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@ -315,10 +338,12 @@ int i915_gem_init_stolen(struct drm_device *dev)
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switch (INTEL_INFO(dev_priv)->gen) {
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case 2:
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case 3:
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break;
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case 4:
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if (!IS_G4X(dev))
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break;
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/* fall through */
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if (IS_G4X(dev))
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g4x_get_stolen_reserved(dev_priv, &reserved_base,
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&reserved_size);
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break;
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case 5:
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/* Assume the gen6 maximum for the older platforms. */
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reserved_size = 1024 * 1024;
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@ -2494,6 +2494,11 @@ enum skl_disp_power_wells {
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#define MCHBAR_MIRROR_BASE_SNB 0x140000
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#define CTG_STOLEN_RESERVED (MCHBAR_MIRROR_BASE + 0x34)
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#define ELK_STOLEN_RESERVED (MCHBAR_MIRROR_BASE + 0x48)
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#define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16)
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#define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
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/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
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#define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)
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