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misc: rtsx: Add power saving functions and fix driving parameter
v4: split power down flow and power saving function to two patch v5: fix up modified change under the --- line Add rts522a L1 sub-state support Save more power on rts5227 rts5249 rts525a rts5260 Fix rts5260 driving parameter Signed-off-by: Ricky Wu <ricky_wu@realtek.com> Link: https://lore.kernel.org/r/20200907100731.7722-1-ricky_wu@realtek.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Ricky Wu
Greg Kroah-Hartman
parent
6010d9befc
commit
7c33e3c4c7
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@ -72,15 +72,80 @@ static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
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pci_read_config_dword(pdev, PCR_SETTING_REG2, ®);
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pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
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if (rtsx_check_mmc_support(reg))
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pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
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pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
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if (rtsx_reg_check_reverse_socket(reg))
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pcr->flags |= PCR_REVERSE_SOCKET;
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}
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static void rts5227_init_from_cfg(struct rtsx_pcr *pcr)
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{
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struct pci_dev *pdev = pcr->pci;
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int l1ss;
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u32 lval;
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struct rtsx_cr_option *option = &pcr->option;
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l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
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if (!l1ss)
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return;
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pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
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if (CHK_PCI_PID(pcr, 0x522A)) {
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if (0 == (lval & 0x0F))
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rtsx_pci_enable_oobs_polling(pcr);
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else
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rtsx_pci_disable_oobs_polling(pcr);
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}
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if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
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rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
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else
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rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
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if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
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rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
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else
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rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
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if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
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rtsx_set_dev_flag(pcr, PM_L1_1_EN);
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else
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rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
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if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
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rtsx_set_dev_flag(pcr, PM_L1_2_EN);
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else
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rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
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if (option->ltr_en) {
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u16 val;
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pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
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if (val & PCI_EXP_DEVCTL2_LTR_EN) {
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option->ltr_enabled = true;
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option->ltr_active = true;
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rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
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} else {
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option->ltr_enabled = false;
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}
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}
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if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
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| PM_L1_1_EN | PM_L1_2_EN))
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option->force_clkreq_0 = false;
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else
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option->force_clkreq_0 = true;
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}
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static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
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{
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u16 cap;
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struct rtsx_cr_option *option = &pcr->option;
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rts5227_init_from_cfg(pcr);
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rtsx_pci_init_cmd(pcr);
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/* Configure GPIO as output */
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@ -102,9 +167,17 @@ static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
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rts5227_fill_driving(pcr, OUTPUT_3V3);
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/* Configure force_clock_req */
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if (pcr->flags & PCR_REVERSE_SOCKET)
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0xB8);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x30);
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else
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0x88);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x00);
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if (option->force_clkreq_0)
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
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FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
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else
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
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FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, pcr->reg_pm_ctrl3, 0x10, 0x00);
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return rtsx_pci_send_cmd(pcr, 100);
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@ -359,6 +432,27 @@ static int rts522a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
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return rtsx_pci_send_cmd(pcr, 100);
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}
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static void rts522a_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
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{
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struct rtsx_cr_option *option = &pcr->option;
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int aspm_L1_1, aspm_L1_2;
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u8 val = 0;
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aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
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aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
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if (active) {
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/* run, latency: 60us */
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if (aspm_L1_1)
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val = option->ltr_l1off_snooze_sspwrgate;
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} else {
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/* l1off, latency: 300us */
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if (aspm_L1_2)
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val = option->ltr_l1off_sspwrgate;
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}
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rtsx_set_l1off_sub(pcr, val);
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}
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/* rts522a operations mainly derived from rts5227, except phy/hw init setting.
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*/
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@ -375,15 +469,29 @@ static const struct pcr_ops rts522a_pcr_ops = {
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.switch_output_voltage = rts522a_switch_output_voltage,
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.cd_deglitch = NULL,
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.conv_clk_and_div_n = NULL,
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.set_l1off_cfg_sub_d0 = rts522a_set_l1off_cfg_sub_d0,
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};
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void rts522a_init_params(struct rtsx_pcr *pcr)
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{
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struct rtsx_cr_option *option = &pcr->option;
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rts5227_init_params(pcr);
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pcr->ops = &rts522a_pcr_ops;
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pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 20, 11);
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pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3;
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option->dev_flags = LTR_L1SS_PWR_GATE_EN;
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option->ltr_en = true;
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/* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
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option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
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option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
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option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
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option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
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option->ltr_l1off_sspwrgate = 0x7F;
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option->ltr_l1off_snooze_sspwrgate = 0x78;
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pcr->option.ocp_en = 1;
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if (pcr->option.ocp_en)
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pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
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@ -73,6 +73,8 @@ static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
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pci_read_config_dword(pdev, PCR_SETTING_REG2, ®);
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pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
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if (rtsx_check_mmc_support(reg))
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pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
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pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
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if (rtsx_reg_check_reverse_socket(reg))
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pcr->flags |= PCR_REVERSE_SOCKET;
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@ -91,6 +93,14 @@ static void rts5249_init_from_cfg(struct rtsx_pcr *pcr)
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pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
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if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
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if (0 == (lval & 0x0F))
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rtsx_pci_enable_oobs_polling(pcr);
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else
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rtsx_pci_disable_oobs_polling(pcr);
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}
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if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
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rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
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@ -130,6 +140,112 @@ static int rts5249_init_from_hw(struct rtsx_pcr *pcr)
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return 0;
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}
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static void rts52xa_save_content_from_efuse(struct rtsx_pcr *pcr)
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{
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u8 cnt, sv;
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u16 j = 0;
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u8 tmp;
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u8 val;
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int i;
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rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
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REG_EFUSE_BYPASS | REG_EFUSE_POR, REG_EFUSE_POR);
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udelay(1);
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pcr_dbg(pcr, "Enable efuse por!");
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pcr_dbg(pcr, "save efuse to autoload");
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rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, REG_EFUSE_ADD_MASK, 0x00);
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rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
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REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
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/* Wait transfer end */
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for (j = 0; j < 1024; j++) {
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rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
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if ((tmp & 0x80) == 0)
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break;
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}
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rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
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cnt = val & 0x0F;
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sv = val & 0x10;
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if (sv) {
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for (i = 0; i < 4; i++) {
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rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
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REG_EFUSE_ADD_MASK, 0x04 + i);
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rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
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REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
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/* Wait transfer end */
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for (j = 0; j < 1024; j++) {
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rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
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if ((tmp & 0x80) == 0)
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break;
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}
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rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
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rtsx_pci_write_register(pcr, 0xFF04 + i, 0xFF, val);
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}
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} else {
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rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr));
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rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8));
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rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr));
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rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8));
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}
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for (i = 0; i < cnt * 4; i++) {
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if (sv)
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rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
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REG_EFUSE_ADD_MASK, 0x08 + i);
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else
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rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
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REG_EFUSE_ADD_MASK, 0x04 + i);
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rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
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REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
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/* Wait transfer end */
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for (j = 0; j < 1024; j++) {
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rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
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if ((tmp & 0x80) == 0)
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break;
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}
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rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
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rtsx_pci_write_register(pcr, 0xFF08 + i, 0xFF, val);
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}
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rtsx_pci_write_register(pcr, 0xFF00, 0xFF, (cnt & 0x7F) | 0x80);
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rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
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REG_EFUSE_BYPASS | REG_EFUSE_POR, REG_EFUSE_BYPASS);
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pcr_dbg(pcr, "Disable efuse por!");
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}
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static void rts52xa_save_content_to_autoload_space(struct rtsx_pcr *pcr)
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{
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u8 val;
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rtsx_pci_read_register(pcr, RESET_LOAD_REG, &val);
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if (val & 0x02) {
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rtsx_pci_read_register(pcr, RTS525A_BIOS_CFG, &val);
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if (val & RTS525A_LOAD_BIOS_FLAG) {
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rtsx_pci_write_register(pcr, RTS525A_BIOS_CFG,
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RTS525A_LOAD_BIOS_FLAG, RTS525A_CLEAR_BIOS_FLAG);
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rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
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REG_EFUSE_POWER_MASK, REG_EFUSE_POWERON);
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pcr_dbg(pcr, "Power ON efuse!");
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mdelay(1);
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rts52xa_save_content_from_efuse(pcr);
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} else {
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rtsx_pci_read_register(pcr, RTS524A_PME_FORCE_CTL, &val);
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if (!(val & 0x08))
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rts52xa_save_content_from_efuse(pcr);
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}
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} else {
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pcr_dbg(pcr, "Load from autoload");
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rtsx_pci_write_register(pcr, 0xFF00, 0xFF, 0x80);
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rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr));
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rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8));
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rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr));
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rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8));
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}
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}
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static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
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{
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struct rtsx_cr_option *option = &(pcr->option);
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@ -139,6 +255,9 @@ static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
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rtsx_pci_init_cmd(pcr);
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if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A))
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rts52xa_save_content_to_autoload_space(pcr);
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/* Rest L1SUB Config */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
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/* Configure GPIO as output */
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@ -157,18 +276,36 @@ static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
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else
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
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rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
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if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
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rtsx_pci_write_register(pcr, REG_VREF, PWD_SUSPND_EN, PWD_SUSPND_EN);
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rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00);
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rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20);
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} else {
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rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x30);
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rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x00);
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}
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/*
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* If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
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* to drive low, and we forcibly request clock.
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*/
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if (option->force_clkreq_0)
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
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rtsx_pci_write_register(pcr, PETXCFG,
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FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
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else
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
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rtsx_pci_write_register(pcr, PETXCFG,
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FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
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return rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
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rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
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if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
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rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
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REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF);
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pcr_dbg(pcr, "Power OFF efuse!");
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}
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return 0;
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}
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static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
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@ -652,6 +789,8 @@ static int rts525a_extra_init_hw(struct rtsx_pcr *pcr)
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{
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rts5249_extra_init_hw(pcr);
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rtsx_pci_write_register(pcr, RTS5250_CLK_CFG3, RTS525A_CFG_MEM_PD, RTS525A_CFG_MEM_PD);
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rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
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||||
if (is_version(pcr, 0x525A, IC_VER_A)) {
|
||||
rtsx_pci_write_register(pcr, L1SUB_CONFIG2,
|
||||
|
|
|
|||
|
|
@ -26,21 +26,17 @@ static u8 rts5260_get_ic_version(struct rtsx_pcr *pcr)
|
|||
|
||||
static void rts5260_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
|
||||
{
|
||||
u8 driving_3v3[6][3] = {
|
||||
{0x94, 0x94, 0x94},
|
||||
{0x11, 0x11, 0x18},
|
||||
{0x55, 0x55, 0x5C},
|
||||
{0x94, 0x94, 0x94},
|
||||
{0x94, 0x94, 0x94},
|
||||
{0xFF, 0xFF, 0xFF},
|
||||
u8 driving_3v3[4][3] = {
|
||||
{0x11, 0x11, 0x11},
|
||||
{0x22, 0x22, 0x22},
|
||||
{0x55, 0x55, 0x55},
|
||||
{0x33, 0x33, 0x33},
|
||||
};
|
||||
u8 driving_1v8[6][3] = {
|
||||
{0x9A, 0x89, 0x89},
|
||||
{0xC4, 0xC4, 0xC4},
|
||||
{0x3C, 0x3C, 0x3C},
|
||||
u8 driving_1v8[4][3] = {
|
||||
{0x35, 0x33, 0x33},
|
||||
{0x8A, 0x88, 0x88},
|
||||
{0xBD, 0xBB, 0xBB},
|
||||
{0x9B, 0x99, 0x99},
|
||||
{0x9A, 0x89, 0x89},
|
||||
{0xFE, 0xFE, 0xFE},
|
||||
};
|
||||
u8 (*driving)[3], drive_sel;
|
||||
|
||||
|
|
@ -58,7 +54,7 @@ static void rts5260_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
|
|||
rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
|
||||
0xFF, driving[drive_sel][1]);
|
||||
|
||||
rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
|
||||
rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
|
||||
0xFF, driving[drive_sel][2]);
|
||||
}
|
||||
|
||||
|
|
@ -82,6 +78,8 @@ static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
|
|||
|
||||
pci_read_config_dword(pdev, PCR_SETTING_REG2, ®);
|
||||
pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
|
||||
if (rtsx_check_mmc_support(reg))
|
||||
pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
|
||||
pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
|
||||
if (rtsx_reg_check_reverse_socket(reg))
|
||||
pcr->flags |= PCR_REVERSE_SOCKET;
|
||||
|
|
@ -559,6 +557,8 @@ static int rts5260_extra_init_hw(struct rtsx_pcr *pcr)
|
|||
rtsx_pci_write_register(pcr, PETXCFG,
|
||||
FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
|
||||
|
||||
rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -18,7 +18,24 @@
|
|||
#define RTS522A_PM_CTRL3 0xFF7E
|
||||
|
||||
#define RTS524A_PME_FORCE_CTL 0xFF78
|
||||
#define REG_EFUSE_BYPASS 0x08
|
||||
#define REG_EFUSE_POR 0x04
|
||||
#define REG_EFUSE_POWER_MASK 0x03
|
||||
#define REG_EFUSE_POWERON 0x03
|
||||
#define REG_EFUSE_POWEROFF 0x00
|
||||
#define RTS5250_CLK_CFG3 0xFF79
|
||||
#define RTS525A_CFG_MEM_PD 0xF0
|
||||
#define RTS524A_PM_CTRL3 0xFF7E
|
||||
#define RTS525A_BIOS_CFG 0xFF2D
|
||||
#define RTS525A_LOAD_BIOS_FLAG 0x01
|
||||
#define RTS525A_CLEAR_BIOS_FLAG 0x00
|
||||
|
||||
#define RTS525A_EFUSE_CTL 0xFC32
|
||||
#define REG_EFUSE_ENABLE 0x80
|
||||
#define REG_EFUSE_MODE 0x40
|
||||
#define RTS525A_EFUSE_ADD 0xFC33
|
||||
#define REG_EFUSE_ADD_MASK 0x3F
|
||||
#define RTS525A_EFUSE_DATA 0xFC35
|
||||
|
||||
#define LTR_ACTIVE_LATENCY_DEF 0x883C
|
||||
#define LTR_IDLE_LATENCY_DEF 0x892C
|
||||
|
|
|
|||
Loading…
Reference in a new issue