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drm/amdgpu: update golden regs for gfx12
update golden regs for gfx12 Signed-off-by: Frank Min <Frank.Min@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 6.11.x
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@ -202,12 +202,16 @@ static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = {
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SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ)
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};
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static const struct soc15_reg_golden golden_settings_gc_12_0[] = {
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static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = {
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SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f),
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SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000),
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SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020)
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};
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static const struct soc15_reg_golden golden_settings_gc_12_0[] = {
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SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000),
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};
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#define DEFAULT_SH_MEM_CONFIG \
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((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
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(SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
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@ -3495,10 +3499,14 @@ static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev)
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switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
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case IP_VERSION(12, 0, 0):
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case IP_VERSION(12, 0, 1):
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soc15_program_register_sequence(adev,
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golden_settings_gc_12_0,
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(const u32)ARRAY_SIZE(golden_settings_gc_12_0));
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if (adev->rev_id == 0)
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soc15_program_register_sequence(adev,
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golden_settings_gc_12_0,
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(const u32)ARRAY_SIZE(golden_settings_gc_12_0));
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golden_settings_gc_12_0_rev0,
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(const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0));
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break;
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default:
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break;
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