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EDAC/{skx_common,i10nm}: Remove the AMAP register for determing DDR5
The configuration flag 'res_config->support_ddr5 = true' sufficiently indicates DDR5 memory support for Sapphire Rapids and Granite Rapids. Additionally, the i10nm_edac driver doesn't need to use the AMAP register for setting the 'fine_grain_bank' of each DIMM. Therefore, remove the AMAP register for determining DDR5. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/all/20240829061309.57738-1-qiuxu.zhuo@intel.com
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@ -47,10 +47,6 @@
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readl((m)->mbase + ((m)->hbm_mc ? 0xef8 : \
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(res_cfg->type == GNR ? 0xaf8 : 0x20ef8)) + \
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(i) * (m)->chan_mmio_sz)
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#define I10NM_GET_AMAP(m, i) \
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readl((m)->mbase + ((m)->hbm_mc ? 0x814 : \
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(res_cfg->type == GNR ? 0xc14 : 0x20814)) + \
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(i) * (m)->chan_mmio_sz)
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#define I10NM_GET_REG32(m, i, offset) \
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readl((m)->mbase + (i) * (m)->chan_mmio_sz + (offset))
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#define I10NM_GET_REG64(m, i, offset) \
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@ -971,7 +967,7 @@ static int i10nm_get_dimm_config(struct mem_ctl_info *mci,
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{
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struct skx_pvt *pvt = mci->pvt_info;
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struct skx_imc *imc = pvt->imc;
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u32 mtr, amap, mcddrtcfg = 0;
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u32 mtr, mcddrtcfg = 0;
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struct dimm_info *dimm;
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int i, j, ndimms;
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@ -980,7 +976,6 @@ static int i10nm_get_dimm_config(struct mem_ctl_info *mci,
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continue;
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ndimms = 0;
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amap = I10NM_GET_AMAP(imc, i);
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if (res_cfg->type != GNR)
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mcddrtcfg = I10NM_GET_MCDDRTCFG(imc, i);
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@ -992,7 +987,7 @@ static int i10nm_get_dimm_config(struct mem_ctl_info *mci,
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mtr, mcddrtcfg, imc->mc, i, j);
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if (IS_DIMM_PRESENT(mtr))
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ndimms += skx_get_dimm_info(mtr, 0, amap, dimm,
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ndimms += skx_get_dimm_info(mtr, 0, 0, dimm,
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imc, i, j, cfg);
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else if (IS_NVDIMM_PRESENT(mcddrtcfg, j))
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ndimms += skx_get_nvdimm_info(dimm, imc, i, j,
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@ -363,7 +363,7 @@ int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
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if (imc->hbm_mc) {
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banks = 32;
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mtype = MEM_HBM2;
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} else if (cfg->support_ddr5 && (amap & 0x8)) {
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} else if (cfg->support_ddr5) {
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banks = 32;
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mtype = MEM_DDR5;
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} else {
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