mirror of
https://github.com/torvalds/linux
synced 2024-09-20 11:07:02 +00:00
arm64: tegra: Device tree fixes for v5.14-rc3
This contains one more fix for SMMU enablement on Tegra194, this time for PCIe. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmDyFesTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoUJuEACMAApbkKbNVc2fNL9OamX5nl6VFUhn S8QTLjyBAv0C6gs7e90LmXzRkOe37pq77a6DHe6gazgwJ485Qgkh/poYADEH5vi8 mLTIns+an+q6pmM1thJQ6QQmDHIrJtqFsiHOfMGT18uVryxbMOCYm2XX93eghEHB HyldsRYpJ/Dhvd0L7WNAMzdxl+HU1Kba1hDamMBd21RacJx5LsvkUie/d25+v+Sw ZC0/+BBCdPaJ6LAiuuROPn1rgSqe4Z/IqZleSHwTaqYjq86GeuQDBM8oMPeki0T7 UiX/vh/th1Cn7OGQbon3EGCo5WGkqU2N6Tj1I8kZlq7TK9xYmcsaiQVRxx5zw8HQ YdY1IF9QnTuKtdFPWlLpBxiiO/z+sybqRtAqr77YdewjmtuRp1HzxD+bWo9ohXLt SIN4+UkijlRUbR5j3lXj+52UacjLnBdbEtygy7e4miqeG76wiskuzTED5tZVJRxd tljd2+7GS4HxA3jBqwBereyflj8Qx8hR0CoVP9wUU+7a45tlvSa8oaAWr1yvzwXC 6qAAsMiiIW6MWJDiaFJRzaXwQw6XLKwo8MgGcKvsUqc21hVxGF8oyjDMDFcvIxjc Xg5oQN4k70PR5N5yUMvc24bMEC2IZ+uo+6R9AiNXXqG3QoGjuM0+fryUvi7LyGmf HmZ74K+nkYaXfQ== =SWvu -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmEH5MAACgkQmmx57+YA GNnneA/7BFZ2n8N6BMy8etumw0XlopnvRRWb9typAw2bdEH78C8X9f+hLaweUEd5 FCACX/gtkejfBcsvpc2hDTI6f7L/vvLBWDauprqXv+6TOpYGpsKAO5oj7MqKpGvL 15EoBoFn1mq1Woje+s07k1CDkYChJuoqYuKAMYMISwC6UHG7DgUzGk4sOJDl5YL4 WiCHOiKxZurTU8iGjBDWGoy8YN6fGplSkpB3OpqPj5gq3vIIXG8KqGl0WkP2ylO2 XxNJRlcbXsKx+0Sq9F0CnhWtccpaxY/GvCGFhvxlB4yrZIZgKEWuxlm/PdiC0Zfq DusJ4cRl2i4GPp1SGnh1kTjjcxPULtXqe8gOk72Wk+wxNW4NIdWKFn+asLhDExE3 fw20s2tpGR/e1AH/Im3s87ZkRykR5ULppWsuOEkaPZRjITr/LSryvhWAikVrUBi1 4LQm1HeemFD36x9CqjSfEoaYyhYU5Z711slTQvo3knxuY1Qm82/hCwPRQSHUe7O6 dLxB/S+P82GUp4g6fEJvqB+JITygEhV5ucGCGBWyp72TnKNBk+qy9bHRby9H29Dh STWDOPT/zlSAcoedlIj468QKrjbhlw/Oa8XvHqGwWaSTwzkI2v4NP+B1o3vsu7+f niAIl3J7uKgFakgsQmyl00MR6Cldp3m74rzu8FEgfN92h7LyBMQ= =aneg -----END PGP SIGNATURE----- Merge tag 'tegra-for-5.14-rc3-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/fixes arm64: tegra: Device tree fixes for v5.14-rc3 This contains one more fix for SMMU enablement on Tegra194, this time for PCIe. * tag 'tegra-for-5.14-rc3-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Enable SMMU support for PCIe on Tegra194 Link: https://lore.kernel.org/r/20210716233858.10096-1-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
79e48a2104
|
@ -1840,7 +1840,11 @@ pcie@14100000 {
|
|||
|
||||
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>,
|
||||
<&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>;
|
||||
interconnect-names = "read", "write";
|
||||
interconnect-names = "dma-mem", "write";
|
||||
iommus = <&smmu TEGRA194_SID_PCIE1>;
|
||||
iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>;
|
||||
iommu-map-mask = <0x0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
pcie@14120000 {
|
||||
|
@ -1890,7 +1894,11 @@ pcie@14120000 {
|
|||
|
||||
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>,
|
||||
<&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>;
|
||||
interconnect-names = "read", "write";
|
||||
interconnect-names = "dma-mem", "write";
|
||||
iommus = <&smmu TEGRA194_SID_PCIE2>;
|
||||
iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>;
|
||||
iommu-map-mask = <0x0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
pcie@14140000 {
|
||||
|
@ -1940,7 +1948,11 @@ pcie@14140000 {
|
|||
|
||||
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>,
|
||||
<&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>;
|
||||
interconnect-names = "read", "write";
|
||||
interconnect-names = "dma-mem", "write";
|
||||
iommus = <&smmu TEGRA194_SID_PCIE3>;
|
||||
iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>;
|
||||
iommu-map-mask = <0x0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
pcie@14160000 {
|
||||
|
@ -1990,7 +2002,11 @@ pcie@14160000 {
|
|||
|
||||
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
|
||||
<&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
|
||||
interconnect-names = "read", "write";
|
||||
interconnect-names = "dma-mem", "write";
|
||||
iommus = <&smmu TEGRA194_SID_PCIE4>;
|
||||
iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
|
||||
iommu-map-mask = <0x0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
pcie@14180000 {
|
||||
|
@ -2040,7 +2056,11 @@ pcie@14180000 {
|
|||
|
||||
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
|
||||
<&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
|
||||
interconnect-names = "read", "write";
|
||||
interconnect-names = "dma-mem", "write";
|
||||
iommus = <&smmu TEGRA194_SID_PCIE0>;
|
||||
iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
|
||||
iommu-map-mask = <0x0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
pcie@141a0000 {
|
||||
|
@ -2094,7 +2114,11 @@ pcie@141a0000 {
|
|||
|
||||
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
|
||||
<&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
|
||||
interconnect-names = "read", "write";
|
||||
interconnect-names = "dma-mem", "write";
|
||||
iommus = <&smmu TEGRA194_SID_PCIE5>;
|
||||
iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
|
||||
iommu-map-mask = <0x0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
pcie_ep@14160000 {
|
||||
|
@ -2127,6 +2151,14 @@ pcie_ep@14160000 {
|
|||
nvidia,aspm-cmrt-us = <60>;
|
||||
nvidia,aspm-pwr-on-t-us = <20>;
|
||||
nvidia,aspm-l0s-entrance-latency-us = <3>;
|
||||
|
||||
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
|
||||
<&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
|
||||
interconnect-names = "dma-mem", "write";
|
||||
iommus = <&smmu TEGRA194_SID_PCIE4>;
|
||||
iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
|
||||
iommu-map-mask = <0x0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
pcie_ep@14180000 {
|
||||
|
@ -2159,6 +2191,14 @@ pcie_ep@14180000 {
|
|||
nvidia,aspm-cmrt-us = <60>;
|
||||
nvidia,aspm-pwr-on-t-us = <20>;
|
||||
nvidia,aspm-l0s-entrance-latency-us = <3>;
|
||||
|
||||
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
|
||||
<&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
|
||||
interconnect-names = "dma-mem", "write";
|
||||
iommus = <&smmu TEGRA194_SID_PCIE0>;
|
||||
iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
|
||||
iommu-map-mask = <0x0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
pcie_ep@141a0000 {
|
||||
|
@ -2194,6 +2234,14 @@ pcie_ep@141a0000 {
|
|||
nvidia,aspm-cmrt-us = <60>;
|
||||
nvidia,aspm-pwr-on-t-us = <20>;
|
||||
nvidia,aspm-l0s-entrance-latency-us = <3>;
|
||||
|
||||
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
|
||||
<&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
|
||||
interconnect-names = "dma-mem", "write";
|
||||
iommus = <&smmu TEGRA194_SID_PCIE5>;
|
||||
iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
|
||||
iommu-map-mask = <0x0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
sram@40000000 {
|
||||
|
|
Loading…
Reference in a new issue