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KVM: MMU: Avoid unnecessary remote tlb flushes when guest updates a pte
If all we're doing is increasing permissions on a pte (typical for demand paging), then there's not need to flush remote tlbs. Worst case they'll get a spurious page fault. Signed-off-by: Avi Kivity <avi@qumranet.com>
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0f74a24c59
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79539cec0c
1 changed files with 26 additions and 1 deletions
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@ -134,6 +134,8 @@ static int dbg = 1;
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#define PT32_DIR_BASE_ADDR_MASK \
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(PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
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#define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
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| PT64_NX_MASK)
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#define PFERR_PRESENT_MASK (1U << 0)
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#define PFERR_WRITE_MASK (1U << 1)
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@ -1227,7 +1229,6 @@ static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
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}
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}
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set_shadow_pte(spte, shadow_trap_nonpresent_pte);
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kvm_flush_remote_tlbs(vcpu->kvm);
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}
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static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
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@ -1250,6 +1251,27 @@ static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
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offset_in_pte);
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}
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static bool need_remote_flush(u64 old, u64 new)
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{
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if (!is_shadow_present_pte(old))
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return false;
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if (!is_shadow_present_pte(new))
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return true;
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if ((old ^ new) & PT64_BASE_ADDR_MASK)
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return true;
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old ^= PT64_NX_MASK;
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new ^= PT64_NX_MASK;
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return (old & ~new & PT64_PERM_MASK) != 0;
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}
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static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, u64 old, u64 new)
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{
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if (need_remote_flush(old, new))
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kvm_flush_remote_tlbs(vcpu->kvm);
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else
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kvm_mmu_flush_tlb(vcpu);
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}
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static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
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{
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u64 *spte = vcpu->last_pte_updated;
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@ -1265,6 +1287,7 @@ void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
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struct hlist_node *node, *n;
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struct hlist_head *bucket;
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unsigned index;
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u64 entry;
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u64 *spte;
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unsigned offset = offset_in_page(gpa);
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unsigned pte_size;
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@ -1335,9 +1358,11 @@ void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
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}
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spte = &page->spt[page_offset / sizeof(*spte)];
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while (npte--) {
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entry = *spte;
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mmu_pte_write_zap_pte(vcpu, page, spte);
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mmu_pte_write_new_pte(vcpu, page, spte, new, bytes,
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page_offset & (pte_size - 1));
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mmu_pte_write_flush_tlb(vcpu, entry, *spte);
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++spte;
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}
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}
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