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https://github.com/torvalds/linux
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[SCSI] qla2xxx: Cleanup some dead-code and make some functions static.
Signed-off-by: Giridhar Malavali <giridhar.malavali@qlogic.com> Signed-off-by: James Bottomley <James.Bottomley@suse.de>
This commit is contained in:
Giridhar Malavali
James Bottomley
parent
35e0cbd4b2
commit
77e334d240
3 changed files with 202 additions and 199 deletions
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@ -501,7 +501,6 @@ extern void qla24xx_wrt_rsp_reg(struct qla_hw_data *, uint16_t, uint16_t);
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/* PCI related functions */
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extern int qla82xx_pci_config(struct scsi_qla_host *);
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extern int qla82xx_pci_mem_read_2M(struct qla_hw_data *, u64, void *, int);
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extern int qla82xx_pci_mem_write_2M(struct qla_hw_data *, u64, void *, int);
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extern char *qla82xx_pci_info_str(struct scsi_qla_host *, char *);
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extern int qla82xx_pci_region_offset(struct pci_dev *, int);
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extern int qla82xx_iospace_config(struct qla_hw_data *);
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@ -509,7 +508,6 @@ extern int qla82xx_iospace_config(struct qla_hw_data *);
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/* Initialization related functions */
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extern void qla82xx_reset_chip(struct scsi_qla_host *);
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extern void qla82xx_config_rings(struct scsi_qla_host *);
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extern int qla82xx_pinit_from_rom(scsi_qla_host_t *);
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extern void qla82xx_watchdog(scsi_qla_host_t *);
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extern int qla82xx_start_firmware(scsi_qla_host_t *);
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@ -534,26 +532,17 @@ extern irqreturn_t qla82xx_msix_default(int, void *);
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extern irqreturn_t qla82xx_msix_rsp_q(int, void *);
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extern void qla82xx_enable_intrs(struct qla_hw_data *);
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extern void qla82xx_disable_intrs(struct qla_hw_data *);
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extern void qla82xx_mbx_completion(scsi_qla_host_t *, uint16_t);
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extern void qla82xx_poll(int, void *);
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extern void qla82xx_init_flags(struct qla_hw_data *);
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/* ISP 8021 hardware related */
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extern void qla82xx_set_drv_active(scsi_qla_host_t *);
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extern int qla82xx_crb_win_lock(struct qla_hw_data *);
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extern void qla82xx_crb_win_unlock(struct qla_hw_data *);
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extern int qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *, ulong *);
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extern int qla82xx_wr_32(struct qla_hw_data *, ulong, u32);
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extern int qla82xx_rd_32(struct qla_hw_data *, ulong);
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extern int qla82xx_rdmem(struct qla_hw_data *, u64, void *, int);
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extern int qla82xx_wrmem(struct qla_hw_data *, u64, void *, int);
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extern int qla82xx_check_for_bad_spd(struct qla_hw_data *);
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extern int qla82xx_load_fw(scsi_qla_host_t *);
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extern int qla82xx_rom_lock(struct qla_hw_data *);
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extern void qla82xx_rom_unlock(struct qla_hw_data *);
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extern int qla82xx_rom_fast_read(struct qla_hw_data *, int , int *);
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extern int qla82xx_do_rom_fast_read(struct qla_hw_data *, int, int *);
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extern unsigned long qla82xx_decode_crb_addr(unsigned long);
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/* ISP 8021 IDC */
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extern void qla82xx_clear_drv_active(struct qla_hw_data *);
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@ -403,6 +403,54 @@ qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off)
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return off;
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}
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static int
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qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off)
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{
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struct crb_128M_2M_sub_block_map *m;
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if (*off >= QLA82XX_CRB_MAX)
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return -1;
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if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
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*off = (*off - QLA82XX_PCI_CAMQM) +
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QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
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return 0;
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}
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if (*off < QLA82XX_PCI_CRBSPACE)
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return -1;
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*off -= QLA82XX_PCI_CRBSPACE;
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/* Try direct map */
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m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
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if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
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*off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
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return 0;
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}
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/* Not in direct map, use crb window */
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return 1;
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}
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#define CRB_WIN_LOCK_TIMEOUT 100000000
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static int qla82xx_crb_win_lock(struct qla_hw_data *ha)
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{
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int done = 0, timeout = 0;
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while (!done) {
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/* acquire semaphore3 from PCI HW block */
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done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
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if (done == 1)
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break;
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if (timeout >= CRB_WIN_LOCK_TIMEOUT)
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return -1;
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timeout++;
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}
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qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum);
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return 0;
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}
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int
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qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data)
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{
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@ -453,24 +501,6 @@ qla82xx_rd_32(struct qla_hw_data *ha, ulong off)
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return data;
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}
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#define CRB_WIN_LOCK_TIMEOUT 100000000
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int qla82xx_crb_win_lock(struct qla_hw_data *ha)
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{
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int done = 0, timeout = 0;
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while (!done) {
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/* acquire semaphore3 from PCI HW block */
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done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
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if (done == 1)
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break;
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if (timeout >= CRB_WIN_LOCK_TIMEOUT)
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return -1;
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timeout++;
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}
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qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum);
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return 0;
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}
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#define IDC_LOCK_TIMEOUT 100000000
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int qla82xx_idc_lock(struct qla_hw_data *ha)
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{
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@ -504,36 +534,6 @@ void qla82xx_idc_unlock(struct qla_hw_data *ha)
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qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
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}
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int
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qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off)
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{
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struct crb_128M_2M_sub_block_map *m;
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if (*off >= QLA82XX_CRB_MAX)
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return -1;
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if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
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*off = (*off - QLA82XX_PCI_CAMQM) +
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QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
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return 0;
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}
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if (*off < QLA82XX_PCI_CRBSPACE)
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return -1;
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*off -= QLA82XX_PCI_CRBSPACE;
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/* Try direct map */
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m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
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if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
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*off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
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return 0;
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}
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/* Not in direct map, use crb window */
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return 1;
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}
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/* PCI Windowing for DDR regions. */
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#define QLA82XX_ADDR_IN_RANGE(addr, low, high) \
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(((addr) <= (high)) && ((addr) >= (low)))
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@ -557,7 +557,7 @@ qla82xx_pci_mem_bound_check(struct qla_hw_data *ha,
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int qla82xx_pci_set_window_warning_count;
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unsigned long
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static unsigned long
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qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr)
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{
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int window;
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@ -798,7 +798,8 @@ qla82xx_pci_mem_write_direct(struct qla_hw_data *ha,
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}
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#define MTU_FUDGE_FACTOR 100
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unsigned long qla82xx_decode_crb_addr(unsigned long addr)
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static unsigned long
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qla82xx_decode_crb_addr(unsigned long addr)
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{
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int i;
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unsigned long base_addr, offset, pci_base;
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@ -824,7 +825,7 @@ unsigned long qla82xx_decode_crb_addr(unsigned long addr)
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static long rom_max_timeout = 100;
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static long qla82xx_rom_lock_timeout = 100;
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int
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static int
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qla82xx_rom_lock(struct qla_hw_data *ha)
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{
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int done = 0, timeout = 0;
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@ -842,7 +843,7 @@ qla82xx_rom_lock(struct qla_hw_data *ha)
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return 0;
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}
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int
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static int
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qla82xx_wait_rom_busy(struct qla_hw_data *ha)
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{
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long timeout = 0;
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@ -862,7 +863,7 @@ qla82xx_wait_rom_busy(struct qla_hw_data *ha)
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return 0;
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}
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int
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static int
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qla82xx_wait_rom_done(struct qla_hw_data *ha)
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{
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long timeout = 0;
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@ -882,7 +883,7 @@ qla82xx_wait_rom_done(struct qla_hw_data *ha)
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return 0;
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}
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int
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static int
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qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
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{
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qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
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@ -905,7 +906,7 @@ qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
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return 0;
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}
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int
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static int
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qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
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{
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int ret, loops = 0;
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@ -926,7 +927,7 @@ qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
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return ret;
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}
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int
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static int
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qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val)
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{
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qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR);
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@ -940,7 +941,7 @@ qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val)
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return 0;
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}
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int
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static int
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qla82xx_flash_wait_write_finish(struct qla_hw_data *ha)
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{
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long timeout = 0;
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@ -964,7 +965,7 @@ qla82xx_flash_wait_write_finish(struct qla_hw_data *ha)
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return ret;
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}
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int
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static int
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qla82xx_flash_set_write_enable(struct qla_hw_data *ha)
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{
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uint32_t val;
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@ -981,7 +982,7 @@ qla82xx_flash_set_write_enable(struct qla_hw_data *ha)
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return 0;
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}
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int
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static int
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qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val)
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{
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if (qla82xx_flash_set_write_enable(ha))
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@ -996,7 +997,7 @@ qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val)
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return qla82xx_flash_wait_write_finish(ha);
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}
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int
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static int
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qla82xx_write_disable_flash(struct qla_hw_data *ha)
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{
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qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI);
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@ -1008,7 +1009,7 @@ qla82xx_write_disable_flash(struct qla_hw_data *ha)
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return 0;
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}
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int
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static int
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ql82xx_rom_lock_d(struct qla_hw_data *ha)
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{
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int loops = 0;
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@ -1024,7 +1025,7 @@ ql82xx_rom_lock_d(struct qla_hw_data *ha)
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return 0;;
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}
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int
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static int
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qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr,
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uint32_t data)
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{
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@ -1061,7 +1062,8 @@ qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr,
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/* This routine does CRB initialize sequence
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* to put the ISP into operational state
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*/
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int qla82xx_pinit_from_rom(scsi_qla_host_t *vha)
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static int
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qla82xx_pinit_from_rom(scsi_qla_host_t *vha)
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{
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int addr, val;
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int i ;
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@ -1207,7 +1209,8 @@ int qla82xx_pinit_from_rom(scsi_qla_host_t *vha)
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return 0;
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}
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int qla82xx_check_for_bad_spd(struct qla_hw_data *ha)
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static int
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qla82xx_check_for_bad_spd(struct qla_hw_data *ha)
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{
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u32 val = 0;
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val = qla82xx_rd_32(ha, BOOT_LOADER_DIMM_STATUS);
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@ -1225,7 +1228,116 @@ int qla82xx_check_for_bad_spd(struct qla_hw_data *ha)
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return 0;
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}
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int
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static int
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qla82xx_pci_mem_write_2M(struct qla_hw_data *ha,
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u64 off, void *data, int size)
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{
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int i, j, ret = 0, loop, sz[2], off0;
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int scale, shift_amount, startword;
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uint32_t temp;
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uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
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/*
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* If not MN, go check for MS or invalid.
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*/
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if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
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mem_crb = QLA82XX_CRB_QDR_NET;
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else {
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mem_crb = QLA82XX_CRB_DDR_NET;
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if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
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return qla82xx_pci_mem_write_direct(ha,
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off, data, size);
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}
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off0 = off & 0x7;
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sz[0] = (size < (8 - off0)) ? size : (8 - off0);
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sz[1] = size - sz[0];
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off8 = off & 0xfffffff0;
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loop = (((off & 0xf) + size - 1) >> 4) + 1;
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shift_amount = 4;
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scale = 2;
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startword = (off & 0xf)/8;
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for (i = 0; i < loop; i++) {
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if (qla82xx_pci_mem_read_2M(ha, off8 +
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(i << shift_amount), &word[i * scale], 8))
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return -1;
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}
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switch (size) {
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case 1:
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tmpw = *((uint8_t *)data);
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break;
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case 2:
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tmpw = *((uint16_t *)data);
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break;
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case 4:
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tmpw = *((uint32_t *)data);
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break;
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case 8:
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default:
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tmpw = *((uint64_t *)data);
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break;
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}
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if (sz[0] == 8) {
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word[startword] = tmpw;
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} else {
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word[startword] &=
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~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
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word[startword] |= tmpw << (off0 * 8);
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}
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if (sz[1] != 0) {
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word[startword+1] &= ~(~0ULL << (sz[1] * 8));
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word[startword+1] |= tmpw >> (sz[0] * 8);
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}
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/*
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* don't lock here - write_wx gets the lock if each time
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* write_lock_irqsave(&adapter->adapter_lock, flags);
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* netxen_nic_pci_change_crbwindow_128M(adapter, 0);
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*/
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for (i = 0; i < loop; i++) {
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temp = off8 + (i << shift_amount);
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qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
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temp = 0;
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qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
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temp = word[i * scale] & 0xffffffff;
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qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
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temp = (word[i * scale] >> 32) & 0xffffffff;
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qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
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temp = word[i*scale + 1] & 0xffffffff;
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qla82xx_wr_32(ha, mem_crb +
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MIU_TEST_AGT_WRDATA_UPPER_LO, temp);
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temp = (word[i*scale + 1] >> 32) & 0xffffffff;
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qla82xx_wr_32(ha, mem_crb +
|
||||
MIU_TEST_AGT_WRDATA_UPPER_HI, temp);
|
||||
|
||||
temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
|
||||
qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
|
||||
temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
|
||||
qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
|
||||
|
||||
for (j = 0; j < MAX_CTL_CHECK; j++) {
|
||||
temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
|
||||
if ((temp & MIU_TA_CTL_BUSY) == 0)
|
||||
break;
|
||||
}
|
||||
|
||||
if (j >= MAX_CTL_CHECK) {
|
||||
if (printk_ratelimit())
|
||||
dev_err(&ha->pdev->dev,
|
||||
"failed to write through agent\n");
|
||||
ret = -1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
qla82xx_fw_load_from_flash(struct qla_hw_data *ha)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -1357,114 +1469,6 @@ qla82xx_pci_mem_read_2M(struct qla_hw_data *ha,
|
|||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
qla82xx_pci_mem_write_2M(struct qla_hw_data *ha,
|
||||
u64 off, void *data, int size)
|
||||
{
|
||||
int i, j, ret = 0, loop, sz[2], off0;
|
||||
int scale, shift_amount, startword;
|
||||
uint32_t temp;
|
||||
uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
|
||||
|
||||
/*
|
||||
* If not MN, go check for MS or invalid.
|
||||
*/
|
||||
if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
|
||||
mem_crb = QLA82XX_CRB_QDR_NET;
|
||||
else {
|
||||
mem_crb = QLA82XX_CRB_DDR_NET;
|
||||
if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
|
||||
return qla82xx_pci_mem_write_direct(ha,
|
||||
off, data, size);
|
||||
}
|
||||
|
||||
off0 = off & 0x7;
|
||||
sz[0] = (size < (8 - off0)) ? size : (8 - off0);
|
||||
sz[1] = size - sz[0];
|
||||
|
||||
off8 = off & 0xfffffff0;
|
||||
loop = (((off & 0xf) + size - 1) >> 4) + 1;
|
||||
shift_amount = 4;
|
||||
scale = 2;
|
||||
startword = (off & 0xf)/8;
|
||||
|
||||
for (i = 0; i < loop; i++) {
|
||||
if (qla82xx_pci_mem_read_2M(ha, off8 +
|
||||
(i << shift_amount), &word[i * scale], 8))
|
||||
return -1;
|
||||
}
|
||||
|
||||
switch (size) {
|
||||
case 1:
|
||||
tmpw = *((uint8_t *)data);
|
||||
break;
|
||||
case 2:
|
||||
tmpw = *((uint16_t *)data);
|
||||
break;
|
||||
case 4:
|
||||
tmpw = *((uint32_t *)data);
|
||||
break;
|
||||
case 8:
|
||||
default:
|
||||
tmpw = *((uint64_t *)data);
|
||||
break;
|
||||
}
|
||||
|
||||
if (sz[0] == 8) {
|
||||
word[startword] = tmpw;
|
||||
} else {
|
||||
word[startword] &=
|
||||
~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
|
||||
word[startword] |= tmpw << (off0 * 8);
|
||||
}
|
||||
if (sz[1] != 0) {
|
||||
word[startword+1] &= ~(~0ULL << (sz[1] * 8));
|
||||
word[startword+1] |= tmpw >> (sz[0] * 8);
|
||||
}
|
||||
|
||||
/*
|
||||
* don't lock here - write_wx gets the lock if each time
|
||||
* write_lock_irqsave(&adapter->adapter_lock, flags);
|
||||
* netxen_nic_pci_change_crbwindow_128M(adapter, 0);
|
||||
*/
|
||||
for (i = 0; i < loop; i++) {
|
||||
temp = off8 + (i << shift_amount);
|
||||
qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
|
||||
temp = 0;
|
||||
qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
|
||||
temp = word[i * scale] & 0xffffffff;
|
||||
qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
|
||||
temp = (word[i * scale] >> 32) & 0xffffffff;
|
||||
qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
|
||||
temp = word[i*scale + 1] & 0xffffffff;
|
||||
qla82xx_wr_32(ha, mem_crb +
|
||||
MIU_TEST_AGT_WRDATA_UPPER_LO, temp);
|
||||
temp = (word[i*scale + 1] >> 32) & 0xffffffff;
|
||||
qla82xx_wr_32(ha, mem_crb +
|
||||
MIU_TEST_AGT_WRDATA_UPPER_HI, temp);
|
||||
|
||||
temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
|
||||
qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
|
||||
temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
|
||||
qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
|
||||
|
||||
for (j = 0; j < MAX_CTL_CHECK; j++) {
|
||||
temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
|
||||
if ((temp & MIU_TA_CTL_BUSY) == 0)
|
||||
break;
|
||||
}
|
||||
|
||||
if (j >= MAX_CTL_CHECK) {
|
||||
if (printk_ratelimit())
|
||||
dev_err(&ha->pdev->dev,
|
||||
"failed to write through agent\n");
|
||||
ret = -1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct qla82xx_uri_table_desc *
|
||||
qla82xx_get_table_desc(const u8 *unirom, int section)
|
||||
|
|
@ -1725,7 +1729,8 @@ void qla82xx_reset_adapter(struct scsi_qla_host *vha)
|
|||
ha->isp_ops->disable_intrs(ha);
|
||||
}
|
||||
|
||||
int qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
|
||||
static int
|
||||
qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
|
||||
{
|
||||
u64 *ptr64;
|
||||
u32 i, flashaddr, size;
|
||||
|
|
@ -1836,7 +1841,8 @@ qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int qla82xx_check_cmdpeg_state(struct qla_hw_data *ha)
|
||||
static int
|
||||
qla82xx_check_cmdpeg_state(struct qla_hw_data *ha)
|
||||
{
|
||||
u32 val = 0;
|
||||
int retries = 60;
|
||||
|
|
@ -1874,7 +1880,8 @@ int qla82xx_check_cmdpeg_state(struct qla_hw_data *ha)
|
|||
return QLA_FUNCTION_FAILED;
|
||||
}
|
||||
|
||||
int qla82xx_check_rcvpeg_state(struct qla_hw_data *ha)
|
||||
static int
|
||||
qla82xx_check_rcvpeg_state(struct qla_hw_data *ha)
|
||||
{
|
||||
u32 val = 0;
|
||||
int retries = 60;
|
||||
|
|
@ -1933,7 +1940,7 @@ static struct qla82xx_legacy_intr_set legacy_intr[] = \
|
|||
* @ha: SCSI driver HA context
|
||||
* @mb0: Mailbox0 register
|
||||
*/
|
||||
void
|
||||
static void
|
||||
qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
|
||||
{
|
||||
uint16_t cnt;
|
||||
|
|
@ -2267,10 +2274,11 @@ qla82xx_set_drv_active(scsi_qla_host_t *vha)
|
|||
|
||||
/* If reset value is all FF's, initialize DRV_ACTIVE */
|
||||
if (drv_active == 0xffffffff) {
|
||||
qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 0);
|
||||
qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE,
|
||||
QLA82XX_DRV_NOT_ACTIVE);
|
||||
drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
|
||||
}
|
||||
drv_active |= (1 << (ha->portnum * 4));
|
||||
drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
|
||||
qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
|
||||
}
|
||||
|
||||
|
|
@ -2280,7 +2288,7 @@ qla82xx_clear_drv_active(struct qla_hw_data *ha)
|
|||
uint32_t drv_active;
|
||||
|
||||
drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
|
||||
drv_active &= ~(1 << (ha->portnum * 4));
|
||||
drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
|
||||
qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
|
||||
}
|
||||
|
||||
|
|
@ -2291,7 +2299,7 @@ qla82xx_need_reset(struct qla_hw_data *ha)
|
|||
int rval;
|
||||
|
||||
drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
|
||||
rval = drv_state & (1 << (ha->portnum * 4));
|
||||
rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
|
||||
return rval;
|
||||
}
|
||||
|
||||
|
|
@ -2305,7 +2313,7 @@ qla82xx_set_rst_ready(struct qla_hw_data *ha)
|
|||
|
||||
/* If reset value is all FF's, initialize DRV_STATE */
|
||||
if (drv_state == 0xffffffff) {
|
||||
qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
|
||||
qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY);
|
||||
drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
|
||||
}
|
||||
drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
|
||||
|
|
@ -2335,7 +2343,8 @@ qla82xx_set_qsnt_ready(struct qla_hw_data *ha)
|
|||
qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
|
||||
}
|
||||
|
||||
int qla82xx_load_fw(scsi_qla_host_t *vha)
|
||||
static int
|
||||
qla82xx_load_fw(scsi_qla_host_t *vha)
|
||||
{
|
||||
int rst;
|
||||
struct fw_blob *blob;
|
||||
|
|
@ -2419,7 +2428,7 @@ qla82xx_start_firmware(scsi_qla_host_t *vha)
|
|||
struct qla_hw_data *ha = vha->hw;
|
||||
|
||||
/* scrub dma mask expansion register */
|
||||
qla82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
|
||||
qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE);
|
||||
|
||||
/* Put both the PEG CMD and RCV PEG to default state
|
||||
* of 0 before resetting the hardware
|
||||
|
|
@ -2869,7 +2878,7 @@ qla82xx_start_scsi(srb_t *sp)
|
|||
return QLA_FUNCTION_FAILED;
|
||||
}
|
||||
|
||||
uint32_t *
|
||||
static uint32_t *
|
||||
qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
|
||||
uint32_t length)
|
||||
{
|
||||
|
|
@ -2890,7 +2899,7 @@ qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
|
|||
return dwptr;
|
||||
}
|
||||
|
||||
int
|
||||
static int
|
||||
qla82xx_unprotect_flash(struct qla_hw_data *ha)
|
||||
{
|
||||
int ret;
|
||||
|
|
@ -2921,7 +2930,7 @@ qla82xx_unprotect_flash(struct qla_hw_data *ha)
|
|||
return ret;
|
||||
}
|
||||
|
||||
int
|
||||
static int
|
||||
qla82xx_protect_flash(struct qla_hw_data *ha)
|
||||
{
|
||||
int ret;
|
||||
|
|
@ -2950,7 +2959,7 @@ qla82xx_protect_flash(struct qla_hw_data *ha)
|
|||
return ret;
|
||||
}
|
||||
|
||||
int
|
||||
static int
|
||||
qla82xx_erase_sector(struct qla_hw_data *ha, int addr)
|
||||
{
|
||||
int ret = 0;
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@
|
|||
#define CRB_RCVPEG_STATE QLA82XX_REG(0x13c)
|
||||
#define BOOT_LOADER_DIMM_STATUS QLA82XX_REG(0x54)
|
||||
#define CRB_DMA_SHIFT QLA82XX_REG(0xcc)
|
||||
#define QLA82XX_DMA_SHIFT_VALUE 0x55555555
|
||||
|
||||
#define QLA82XX_HW_H0_CH_HUB_ADR 0x05
|
||||
#define QLA82XX_HW_H1_CH_HUB_ADR 0x0E
|
||||
|
|
@ -583,6 +584,10 @@
|
|||
#define QLA82XX_DRVST_RST_RDY 1
|
||||
#define QLA82XX_DRVST_QSNT_RDY 2
|
||||
|
||||
/* Different drive active state */
|
||||
#define QLA82XX_DRV_NOT_ACTIVE 0
|
||||
#define QLA82XX_DRV_ACTIVE 1
|
||||
|
||||
/*
|
||||
* The PCI VendorID and DeviceID for our board.
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in a new issue