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riscv: add support for kernel-mode FPU
This is motivated by the amdgpu DRM driver, which needs floating-point code to support recent hardware. That code is not performance-critical, so only provide a minimal non-preemptible implementation for now. Support is limited to riscv64 because riscv32 requires runtime (libgcc) assistance to convert between doubles and 64-bit integers. Link: https://lkml.kernel.org/r/20240329072441.591471-12-samuel.holland@sifive.com Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Acked-by: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Borislav Petkov (AMD) <bp@alien8.de> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Huacai Chen <chenhuacai@kernel.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jonathan Corbet <corbet@lwn.net> Cc: Masahiro Yamada <masahiroy@kernel.org> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nathan Chancellor <nathan@kernel.org> Cc: Nicolas Schier <nicolas@fjasle.eu> Cc: Russell King <linux@armlinux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: WANG Xuerui <git@xen0n.name> Cc: Will Deacon <will@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
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@ -27,6 +27,7 @@ config RISCV
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select ARCH_HAS_GCOV_PROFILE_ALL
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select ARCH_HAS_GIGANTIC_PAGE
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select ARCH_HAS_KCOV
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select ARCH_HAS_KERNEL_FPU_SUPPORT if 64BIT && FPU
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select ARCH_HAS_MEMBARRIER_CALLBACKS
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select ARCH_HAS_MEMBARRIER_SYNC_CORE
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select ARCH_HAS_MMIOWB
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@ -84,6 +84,9 @@ KBUILD_CFLAGS += -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64i
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KBUILD_AFLAGS += -march=$(riscv-march-y)
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# For C code built with floating-point support, exclude V but keep F and D.
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CC_FLAGS_FPU := -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)([^v_]*)v?/\1\2/')
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KBUILD_CFLAGS += -mno-save-restore
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KBUILD_CFLAGS += -DCONFIG_PAGE_OFFSET=$(CONFIG_PAGE_OFFSET)
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16
arch/riscv/include/asm/fpu.h
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arch/riscv/include/asm/fpu.h
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@ -0,0 +1,16 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2023 SiFive
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*/
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#ifndef _ASM_RISCV_FPU_H
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#define _ASM_RISCV_FPU_H
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#include <asm/switch_to.h>
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#define kernel_fpu_available() has_fpu()
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void kernel_fpu_begin(void);
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void kernel_fpu_end(void);
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#endif /* ! _ASM_RISCV_FPU_H */
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@ -67,6 +67,7 @@ obj-$(CONFIG_RISCV_MISALIGNED) += unaligned_access_speed.o
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obj-$(CONFIG_RISCV_PROBE_UNALIGNED_ACCESS) += copy-unaligned.o
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obj-$(CONFIG_FPU) += fpu.o
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obj-$(CONFIG_FPU) += kernel_mode_fpu.o
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obj-$(CONFIG_RISCV_ISA_V) += vector.o
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obj-$(CONFIG_RISCV_ISA_V) += kernel_mode_vector.o
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obj-$(CONFIG_SMP) += smpboot.o
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28
arch/riscv/kernel/kernel_mode_fpu.c
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arch/riscv/kernel/kernel_mode_fpu.c
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@ -0,0 +1,28 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2023 SiFive
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*/
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#include <linux/export.h>
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#include <linux/preempt.h>
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#include <asm/csr.h>
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#include <asm/fpu.h>
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#include <asm/processor.h>
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#include <asm/switch_to.h>
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void kernel_fpu_begin(void)
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{
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preempt_disable();
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fstate_save(current, task_pt_regs(current));
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csr_set(CSR_SSTATUS, SR_FS);
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}
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EXPORT_SYMBOL_GPL(kernel_fpu_begin);
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void kernel_fpu_end(void)
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{
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csr_clear(CSR_SSTATUS, SR_FS);
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fstate_restore(current, task_pt_regs(current));
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preempt_enable();
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}
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EXPORT_SYMBOL_GPL(kernel_fpu_end);
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