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MIPS: Add new GIC clocksource.
Add new clocksource that uses the counter present on the MIPS Global Interrupt Controller. Signed-off-by: Steven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4681/ Signed-off-by: John Crispin <blogic@openwrt.org>
This commit is contained in:
Steven J. Hill
John Crispin
parent
4cb764b454
commit
778eeb1b19
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@ -296,6 +296,7 @@ config MIPS_MALTA
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select BOOT_RAW
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select CEVT_R4K
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select CSRC_R4K
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select CSRC_GIC
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select DMA_NONCOHERENT
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select GENERIC_ISA_DMA
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select HAVE_PCSPKR_PLATFORM
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@ -928,6 +929,9 @@ config CSRC_POWERTV
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config CSRC_R4K
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bool
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config CSRC_GIC
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bool
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config CSRC_SB1250
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bool
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@ -359,6 +359,7 @@ struct gic_shared_intr_map {
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/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
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#define GIC_PIN_TO_VEC_OFFSET (1)
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extern int gic_present;
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extern unsigned long _gic_base;
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extern unsigned int gic_irq_base;
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extern unsigned int gic_irq_flags[];
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@ -75,7 +75,7 @@ extern int init_r4k_clocksource(void);
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static inline int init_mips_clocksource(void)
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{
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#ifdef CONFIG_CSRC_R4K
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#if defined(CONFIG_CSRC_R4K) && !defined(CONFIG_CSRC_GIC)
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return init_r4k_clocksource();
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#else
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return 0;
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@ -27,6 +27,7 @@ obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o
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obj-$(CONFIG_CSRC_POWERTV) += csrc-powertv.o
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obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o
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obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o
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obj-$(CONFIG_CSRC_GIC) += csrc-gic.o
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obj-$(CONFIG_SYNC_R4K) += sync-r4k.o
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obj-$(CONFIG_STACKTRACE) += stacktrace.o
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49
arch/mips/kernel/csrc-gic.c
Normal file
49
arch/mips/kernel/csrc-gic.c
Normal file
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@ -0,0 +1,49 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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*/
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#include <linux/clocksource.h>
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#include <linux/init.h>
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#include <asm/time.h>
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#include <asm/gic.h>
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static cycle_t gic_hpt_read(struct clocksource *cs)
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{
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unsigned int hi, hi2, lo;
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do {
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GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi);
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GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), lo);
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GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi2);
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} while (hi2 != hi);
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return (((cycle_t) hi) << 32) + lo;
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}
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static struct clocksource gic_clocksource = {
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.name = "GIC",
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.read = gic_hpt_read,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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void __init gic_clocksource_init(unsigned int frequency)
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{
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unsigned int config, bits;
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/* Calculate the clocksource mask. */
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GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), config);
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bits = 32 + ((config & GIC_SH_CONFIG_COUNTBITS_MSK) >>
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(GIC_SH_CONFIG_COUNTBITS_SHF - 2));
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/* Set clocksource mask. */
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gic_clocksource.mask = CLOCKSOURCE_MASK(bits);
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/* Calculate a somewhat reasonable rating value. */
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gic_clocksource.rating = 200 + frequency / 10000000;
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clocksource_register_hz(&gic_clocksource, frequency);
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}
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@ -17,7 +17,6 @@
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*
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* Setting up the clock on the MIPS boards.
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*/
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#include <linux/types.h>
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#include <linux/i8253.h>
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#include <linux/init.h>
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@ -25,7 +24,6 @@
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/time.h>
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#include <linux/timex.h>
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#include <linux/mc146818rtc.h>
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@ -34,11 +32,11 @@
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#include <asm/hardirq.h>
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#include <asm/irq.h>
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#include <asm/div64.h>
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#include <asm/cpu.h>
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#include <asm/setup.h>
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#include <asm/time.h>
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#include <asm/mc146818-time.h>
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#include <asm/msc01_ic.h>
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#include <asm/gic.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/mips-boards/prom.h>
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@ -46,6 +44,7 @@
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#include <asm/mips-boards/maltaint.h>
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unsigned long cpu_khz;
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int gic_frequency;
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static int mips_cpu_timer_irq;
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static int mips_cpu_perf_irq;
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@ -61,44 +60,50 @@ static void mips_perf_dispatch(void)
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do_IRQ(mips_cpu_perf_irq);
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}
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/*
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* Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
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*/
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static unsigned int __init estimate_cpu_frequency(void)
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static unsigned int freqround(unsigned int freq, unsigned int amount)
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{
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unsigned int prid = read_c0_prid() & 0xffff00;
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unsigned int count;
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freq += amount;
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freq -= freq % (amount*2);
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return freq;
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}
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/*
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* Estimate CPU and GIC frequencies.
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*/
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static void __init estimate_frequencies(void)
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{
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unsigned long flags;
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unsigned int start;
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unsigned int count, start;
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unsigned int giccount = 0, gicstart = 0;
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local_irq_save(flags);
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/* Start counter exactly on falling edge of update flag */
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/* Start counter exactly on falling edge of update flag. */
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while (CMOS_READ(RTC_REG_A) & RTC_UIP);
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while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
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/* Start r4k counter. */
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/* Initialize counters. */
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start = read_c0_count();
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if (gic_present)
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GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), gicstart);
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/* Read counter exactly on falling edge of update flag */
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/* Read counter exactly on falling edge of update flag. */
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while (CMOS_READ(RTC_REG_A) & RTC_UIP);
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while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
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count = read_c0_count() - start;
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count = read_c0_count();
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if (gic_present)
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GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), giccount);
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/* restore interrupts */
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local_irq_restore(flags);
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count -= start;
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if (gic_present)
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giccount -= gicstart;
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mips_hpt_frequency = count;
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if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
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(prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
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count *= 2;
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count += 5000; /* round */
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count -= count%10000;
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return count;
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if (gic_present)
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gic_frequency = giccount;
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}
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void read_persistent_clock(struct timespec *ts)
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@ -144,22 +149,34 @@ unsigned int __cpuinit get_c0_compare_int(void)
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void __init plat_time_init(void)
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{
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unsigned int est_freq;
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unsigned int prid = read_c0_prid() & 0xffff00;
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unsigned int freq;
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/* Set Data mode - binary. */
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CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
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estimate_frequencies();
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est_freq = estimate_cpu_frequency();
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freq = mips_hpt_frequency;
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if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
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(prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
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freq *= 2;
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freq = freqround(freq, 5000);
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pr_debug("CPU frequency %d.%02d MHz\n", freq/1000000,
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(freq%1000000)*100/1000000);
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cpu_khz = freq / 1000;
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printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
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(est_freq%1000000)*100/1000000);
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if (gic_present) {
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freq = freqround(gic_frequency, 5000);
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pr_debug("GIC frequency %d.%02d MHz\n", freq/1000000,
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(freq%1000000)*100/1000000);
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gic_clocksource_init(gic_frequency);
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} else
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init_r4k_clocksource();
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cpu_khz = est_freq / 1000;
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mips_scroll_message();
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#ifdef CONFIG_I8253 /* Only Malta has a PIT */
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#ifdef CONFIG_I8253
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/* Only Malta has a PIT. */
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setup_pit_timer();
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#endif
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mips_scroll_message();
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plat_perf_setup();
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}
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