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mmc: sdhci: Parameterize ADMA sizes and alignment
In preparation for 64-bit ADMA, parameterize ADMA sizes and alignment. 64-bit ADMA has a larger descriptor because it contains a 64-bit address instead of a 32-bit address. Also data must be 8-byte aligned instead of 4-byte aligned. Consequently, sdhci_host members are added for descriptor, table, and buffer sizes and alignment. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Adrian Hunter
Ulf Hansson
parent
1c3d5f6ddc
commit
76fe379aca
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@ -44,14 +44,6 @@
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#define MAX_TUNING_LOOP 40
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/*
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* The ADMA2 descriptor table size is calculated as the maximum number of
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* segments (128), times 2 to allow for an alignment descriptor for each
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* segment, plus 1 for a nop end descriptor, all multipled by the 32-bit
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* descriptor size (8).
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*/
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#define ADMA_SIZE ((128 * 2 + 1) * 8)
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static unsigned int debug_quirks = 0;
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static unsigned int debug_quirks2;
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@ -502,10 +494,10 @@ static int sdhci_adma_table_pre(struct sdhci_host *host,
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direction = DMA_TO_DEVICE;
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host->align_addr = dma_map_single(mmc_dev(host->mmc),
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host->align_buffer, 128 * 4, direction);
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host->align_buffer, host->align_buffer_sz, direction);
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if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
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goto fail;
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BUG_ON(host->align_addr & 0x3);
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BUG_ON(host->align_addr & host->align_mask);
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host->sg_count = dma_map_sg(mmc_dev(host->mmc),
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data->sg, data->sg_len, direction);
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@ -528,7 +520,8 @@ static int sdhci_adma_table_pre(struct sdhci_host *host,
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* the (up to three) bytes that screw up the
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* alignment.
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*/
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offset = (4 - (addr & 0x3)) & 0x3;
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offset = (host->align_sz - (addr & host->align_mask)) &
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host->align_mask;
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if (offset) {
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if (data->flags & MMC_DATA_WRITE) {
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buffer = sdhci_kmap_atomic(sg, &flags);
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@ -543,10 +536,10 @@ static int sdhci_adma_table_pre(struct sdhci_host *host,
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BUG_ON(offset > 65536);
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align += 4;
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align_addr += 4;
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align += host->align_sz;
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align_addr += host->align_sz;
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desc += 8;
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desc += host->desc_sz;
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addr += offset;
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len -= offset;
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@ -556,13 +549,13 @@ static int sdhci_adma_table_pre(struct sdhci_host *host,
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/* tran, valid */
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sdhci_adma_write_desc(desc, addr, len, 0x21);
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desc += 8;
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desc += host->desc_sz;
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/*
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* If this triggers then we have a calculation bug
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* somewhere. :/
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*/
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WARN_ON((desc - host->adma_table) >= ADMA_SIZE);
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WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
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}
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if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
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@ -570,7 +563,7 @@ static int sdhci_adma_table_pre(struct sdhci_host *host,
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* Mark the last descriptor as the terminating descriptor
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*/
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if (desc != host->adma_table) {
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desc -= 8;
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desc -= host->desc_sz;
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sdhci_adma_mark_end(desc);
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}
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} else {
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@ -587,14 +580,14 @@ static int sdhci_adma_table_pre(struct sdhci_host *host,
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*/
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if (data->flags & MMC_DATA_WRITE) {
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dma_sync_single_for_device(mmc_dev(host->mmc),
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host->align_addr, 128 * 4, direction);
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host->align_addr, host->align_buffer_sz, direction);
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}
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return 0;
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unmap_align:
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dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
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128 * 4, direction);
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host->align_buffer_sz, direction);
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fail:
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return -EINVAL;
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}
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@ -617,12 +610,12 @@ static void sdhci_adma_table_post(struct sdhci_host *host,
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direction = DMA_TO_DEVICE;
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dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
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128 * 4, direction);
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host->align_buffer_sz, direction);
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/* Do a quick scan of the SG list for any unaligned mappings */
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has_unaligned = false;
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for_each_sg(data->sg, sg, host->sg_count, i)
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if (sg_dma_address(sg) & 3) {
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if (sg_dma_address(sg) & host->align_mask) {
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has_unaligned = true;
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break;
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}
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@ -634,8 +627,9 @@ static void sdhci_adma_table_post(struct sdhci_host *host,
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align = host->align_buffer;
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for_each_sg(data->sg, sg, host->sg_count, i) {
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if (sg_dma_address(sg) & 0x3) {
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size = 4 - (sg_dma_address(sg) & 0x3);
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if (sg_dma_address(sg) & host->align_mask) {
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size = host->align_sz -
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(sg_dma_address(sg) & host->align_mask);
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buffer = sdhci_kmap_atomic(sg, &flags);
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WARN_ON(((long)buffer & (PAGE_SIZE - 1)) >
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@ -643,7 +637,7 @@ static void sdhci_adma_table_post(struct sdhci_host *host,
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memcpy(buffer, align, size);
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sdhci_kunmap_atomic(buffer, &flags);
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align += 4;
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align += host->align_sz;
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}
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}
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}
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@ -2316,7 +2310,7 @@ static void sdhci_adma_show_error(struct sdhci_host *host)
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DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
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name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
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desc += 8;
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desc += host->desc_sz;
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if (attr & 2)
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break;
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@ -2878,17 +2872,23 @@ int sdhci_add_host(struct sdhci_host *host)
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if (host->flags & SDHCI_USE_ADMA) {
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/*
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* We need to allocate descriptors for all sg entries
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* (128) and potentially one alignment transfer for
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* each of those entries.
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* The DMA descriptor table size is calculated as the maximum
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* number of segments times 2, to allow for an alignment
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* descriptor for each segment, plus 1 for a nop end descriptor,
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* all multipled by the descriptor size.
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*/
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host->adma_table_sz = (128 * 2 + 1) * 8;
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host->align_buffer_sz = 128 * 4;
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host->desc_sz = 8;
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host->align_sz = 4;
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host->align_mask = 3;
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host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
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ADMA_SIZE,
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host->adma_table_sz,
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&host->adma_addr,
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GFP_KERNEL);
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host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
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host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
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if (!host->adma_table || !host->align_buffer) {
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dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
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dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
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host->adma_table, host->adma_addr);
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kfree(host->align_buffer);
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pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
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@ -2896,11 +2896,11 @@ int sdhci_add_host(struct sdhci_host *host)
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host->flags &= ~SDHCI_USE_ADMA;
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host->adma_table = NULL;
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host->align_buffer = NULL;
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} else if (host->adma_addr & 3) {
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} else if (host->adma_addr & host->align_mask) {
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pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
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mmc_hostname(mmc));
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host->flags &= ~SDHCI_USE_ADMA;
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dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
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dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
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host->adma_table, host->adma_addr);
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kfree(host->align_buffer);
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host->adma_table = NULL;
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@ -3360,7 +3360,7 @@ void sdhci_remove_host(struct sdhci_host *host, int dead)
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regulator_disable(mmc->supply.vqmmc);
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if (host->adma_table)
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dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
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dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
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host->adma_table, host->adma_addr);
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kfree(host->align_buffer);
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@ -158,9 +158,16 @@ struct sdhci_host {
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void *adma_table; /* ADMA descriptor table */
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void *align_buffer; /* Bounce buffer */
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size_t adma_table_sz; /* ADMA descriptor table size */
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size_t align_buffer_sz; /* Bounce buffer size */
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dma_addr_t adma_addr; /* Mapped ADMA descr. table */
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dma_addr_t align_addr; /* Mapped bounce buffer */
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unsigned int desc_sz; /* ADMA descriptor size */
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unsigned int align_sz; /* ADMA alignment */
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unsigned int align_mask; /* ADMA alignment mask */
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struct tasklet_struct finish_tasklet; /* Tasklet structures */
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struct timer_list timer; /* Timer for timeouts */
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