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Revert "powerpc/usb: fix issue of CPU halt when missing USB PHY clock"

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This reverts commit 529febeee6.

To quote Dirk:
	This commit introduces a check for the USB PHY clock.
	Problem is that CTRL_PHY_CLK_VALID bit seems not to be present
	on all Freescale ehci implementations, at least P1022 does not
	have it.  So this check always fails and the driver never gets
	loaded.

So we need to revert this patch.

Reported-by: Dirk Eibach <Eibach@gdsys.de>
Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Cc: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Greg Kroah-Hartman 2012-03-02 16:08:54 -08:00
parent 45196cee28
commit 71919403dc
2 changed files with 2 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
drivers/usb/host/ehci-fsl.c
View file

@ -239,7 +239,7 @@ static void ehci_fsl_setup_phy(struct ehci_hcd *ehci,
ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
}
static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
{
struct usb_hcd *hcd = ehci_to_hcd(ehci);
struct fsl_usb2_platform_data *pdata;
@ -299,19 +299,12 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
#endif
out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001);
}
if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & CTRL_PHY_CLK_VALID)) {
printk(KERN_WARNING "fsl-ehci: USB PHY clock invalid\n");
return -ENODEV;
}
return 0;
}
/* called after powerup, by probe or system-pm "wakeup" */
static int ehci_fsl_reinit(struct ehci_hcd *ehci)
{
if (ehci_fsl_usb_setup(ehci))
return -ENODEV;
ehci_fsl_usb_setup(ehci);
ehci_port_power(ehci, 0);
return 0;

1
drivers/usb/host/ehci-fsl.h
View file

@ -45,6 +45,5 @@
#define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
#define CTRL_PHY_CLK_VALID (1 << 17)
#define SNOOP_SIZE_2GB 0x1e
#endif /* _EHCI_FSL_H */