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Renesas ARM DT updates for v5.19

Browse source 
- ADC, SDHI, CAN-FD, I2C, QSPI, timer, watchdog, sound, USB, SPI, GPU,
     cpufreq, and thermal support for the RZ/V2L SoC, and the RZ/V2L
     SMARC EVK development board,
   - USB, I2C, Audio, NOR Flash, timer, SPI support for RZ/G2LC SMARC EVK
     development board,
   - Can-FD support for the R-Car M30W+ and V3U SoCs, and the Falcon
     development board,
   - I2C and GPIO support for the R-Car S4-8 SoC,
   - I2C EEPROM support for the Falcon development board,
   - SPI Multi I/O Bus Controller (RPC-IF) support for the R-Car H3,
     M3-W(+), M3-N, E3, and D3 SoCs,
   - RPC HyperFlash support for the Draak, Ebisu, Salvator-X(S), and ULCB
     development boards,
   - Initial support (UART, DMAC, pin control, SDHI, eMMC, Ethernet) for
     the RZ/G2UL SoC, and the RZ/G2UL SMARC EVK development board,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-arm-dt-for-v5.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM DT updates for v5.19

  - ADC, SDHI, CAN-FD, I2C, QSPI, timer, watchdog, sound, USB, SPI, GPU,
    cpufreq, and thermal support for the RZ/V2L SoC, and the RZ/V2L
    SMARC EVK development board,
  - USB, I2C, Audio, NOR Flash, timer, SPI support for RZ/G2LC SMARC EVK
    development board,
  - Can-FD support for the R-Car M30W+ and V3U SoCs, and the Falcon
    development board,
  - I2C and GPIO support for the R-Car S4-8 SoC,
  - I2C EEPROM support for the Falcon development board,
  - SPI Multi I/O Bus Controller (RPC-IF) support for the R-Car H3,
    M3-W(+), M3-N, E3, and D3 SoCs,
  - RPC HyperFlash support for the Draak, Ebisu, Salvator-X(S), and ULCB
    development boards,
  - Initial support (UART, DMAC, pin control, SDHI, eMMC, Ethernet) for
    the RZ/G2UL SoC, and the RZ/G2UL SMARC EVK development board,
  - Miscellaneous fixes and improvements.

* tag 'renesas-arm-dt-for-v5.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (55 commits)
  ARM: dts: r9a06g032: Drop "arm,cortex-a7-timer" from timer node
  arm64: dts: renesas: r8a779f0: Add GPIO nodes
  arm64: dts: renesas: rzg2ul-smarc-som: Enable Ethernet on SMARC platform
  arm64: dts: renesas: rzg2ul-smarc-som: Enable eMMC on SMARC platform
  arm64: dts: renesas: rzg2ul-smarc: Enable microSD on SMARC platform
  arm64: dts: renesas: r9a07g043: Add GbEthernet nodes
  arm64: dts: renesas: r9a07g043: Add SDHI nodes
  arm64: dts: renesas: rzg2ul-smarc: Add scif0 and audio clk pins
  arm64: dts: renesas: r9a07g043: Fillup the pinctrl stub node
  arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC EVK
  arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC
  arm64: dts: renesas: rzg2l-smarc: Move gpios property of vccq_sdhi1 from common dtsi
  arm64: dts: renesas: rzg2lc-smarc: Enable RSPI1 on carrier board
  arm64: dts: renesas: ulcb: Add RPC HyperFlash device node
  arm64: dts: renesas: salvator-common: Add RPC HyperFlash device node
  arm64: dts: renesas: ebisu: Add RPC HyperFlash device node
  arm64: dts: renesas: draak: Add RPC HyperFlash device node
  arm64: dts: renesas: rcar-gen3: Add RPC device nodes
  arm64: dts: renesas: rcar-gen4: Add interrupt properties to watchdog nodes
  arm64: dts: renesas: rzg2: Add interrupt properties to watchdog nodes
  ...

Link: https://lore.kernel.org/r/cover.1650638505.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-05-03 15:24:08 +02:00
parent 9c099a379c aa70cbda74
commit 70a89009f7
47 changed files with 2457 additions and 141 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
arch/arm/boot/dts/r8a7743.dtsi
View file

@ -140,6 +140,7 @@ rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7743-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 402>;

1
arch/arm/boot/dts/r8a7744.dtsi
View file

@ -140,6 +140,7 @@ rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7744-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
resets = <&cpg 402>;

1
arch/arm/boot/dts/r8a7745.dtsi
View file

@ -270,6 +270,7 @@ rst: reset-controller@e6160000 {
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7745-wdt",
"renesas,rcar-gen2-wdt";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;

1
arch/arm/boot/dts/r8a77470.dtsi
View file

@ -91,6 +91,7 @@ rwdt: watchdog@e6020000 {
compatible = "renesas,r8a77470-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
resets = <&cpg 402>;

1
arch/arm/boot/dts/r8a7790.dtsi
View file

@ -274,6 +274,7 @@ rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7790-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 402>;

1
arch/arm/boot/dts/r8a7791.dtsi
View file

@ -161,6 +161,7 @@ rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7791-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 402>;

1
arch/arm/boot/dts/r8a7792.dtsi
View file

@ -111,6 +111,7 @@ rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7792-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 402>;

1
arch/arm/boot/dts/r8a7793.dtsi
View file

@ -146,6 +146,7 @@ rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7793-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
resets = <&cpg 402>;

1
arch/arm/boot/dts/r8a7794.dtsi
View file

@ -128,6 +128,7 @@ rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7794-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
resets = <&cpg 402>;

3
arch/arm/boot/dts/r9a06g032.dtsi
View file

@ -214,8 +214,7 @@ gic: interrupt-controller@44101000 {
};
timer {
compatible = "arm,cortex-a7-timer",
"arm,armv7-timer";
compatible = "arm,armv7-timer";
interrupt-parent = <&gic>;
arm,cpu-registers-not-fw-configured;
always-on;

2
arch/arm64/boot/dts/renesas/Makefile
View file

@ -75,6 +75,8 @@ dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb

58
arch/arm64/boot/dts/renesas/draak.dtsi
View file

@ -541,6 +541,12 @@ pwm1_pins: pwm1 {
function = "pwm1";
};
rpc_pins: rpc {
groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset",
"rpc_int";
function = "rpc";
};
scif2_pins: scif2 {
groups = "scif2_data";
function = "scif2";
@ -630,6 +636,58 @@ rsnd_for_ak4613: endpoint {
};
};
&rpc {
pinctrl-0 = <&rpc_pins>;
pinctrl-names = "default";
/* Left disabled. To be enabled by firmware when unlocked. */
flash@0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
bl2@40000 {
reg = <0x00040000 0x140000>;
read-only;
};
cert_header_sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x040000>;
read-only;
};
tee@200000 {
reg = <0x00200000 0x440000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x100000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";

58
arch/arm64/boot/dts/renesas/ebisu.dtsi
View file

@ -600,6 +600,12 @@ pwm5_pins: pwm5 {
function = "pwm5";
};
rpc_pins: rpc {
groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset",
"rpc_int";
function = "rpc";
};
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
@ -711,6 +717,58 @@ dai0 {
};
&rpc {
pinctrl-0 = <&rpc_pins>;
pinctrl-names = "default";
/* Left disabled. To be enabled by firmware when unlocked. */
flash@0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
bl2@40000 {
reg = <0x00040000 0x140000>;
read-only;
};
cert_header_sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x040000>;
read-only;
};
tee@200000 {
reg = <0x00200000 0x440000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x100000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";

1
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
View file

@ -283,6 +283,7 @@ rwdt: watchdog@e6020000 {
compatible = "renesas,r8a774a1-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 402>;

1
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
View file

@ -156,6 +156,7 @@ rwdt: watchdog@e6020000 {
compatible = "renesas,r8a774b1-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 402>;

1
arch/arm64/boot/dts/renesas/r8a774c0.dtsi
View file

@ -145,6 +145,7 @@ rwdt: watchdog@e6020000 {
compatible = "renesas,r8a774c0-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 402>;

17
arch/arm64/boot/dts/renesas/r8a77951.dtsi
View file

@ -369,6 +369,7 @@ soc: soc {
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@ -2731,6 +2732,22 @@ sdhi3: mmc@ee160000 {
status = "disabled";
};
rpc: spi@ee200000 {
compatible = "renesas,r8a7795-rpc-if",
"renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x200>,
<0 0x08000000 0 0x04000000>,
<0 0xee208000 0 0x100>;
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
sata: sata@ee300000 {
compatible = "renesas,sata-r8a7795",
"renesas,rcar-gen3-sata";

17
arch/arm64/boot/dts/renesas/r8a77960.dtsi
View file

@ -334,6 +334,7 @@ rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7796-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@ -2531,6 +2532,22 @@ sdhi3: mmc@ee160000 {
status = "disabled";
};
rpc: spi@ee200000 {
compatible = "renesas,r8a7796-rpc-if",
"renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x200>,
<0 0x08000000 0 0x04000000>,
<0 0xee208000 0 0x100>;
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;

42
arch/arm64/boot/dts/renesas/r8a77961.dtsi
View file

@ -323,6 +323,7 @@ rwdt: watchdog@e6020000 {
compatible = "renesas,r8a77961-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@ -1222,6 +1223,31 @@ can1: can@e6c38000 {
status = "disabled";
};
canfd: can@e66c0000 {
compatible = "renesas,r8a77961-canfd",
"renesas,rcar-gen3-canfd";
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A77961_CLK_CANFD>,
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";
channel0 {
status = "disabled";
};
channel1 {
status = "disabled";
};
};
pwm0: pwm@e6e30000 {
compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 8>;
@ -2375,6 +2401,22 @@ sdhi3: mmc@ee160000 {
status = "disabled";
};
rpc: spi@ee200000 {
compatible = "renesas,r8a77961-rpc-if",
"renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x200>,
<0 0x08000000 0 0x04000000>,
<0 0xee208000 0 0x100>;
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;

17
arch/arm64/boot/dts/renesas/r8a77965.dtsi
View file

@ -205,6 +205,7 @@ rwdt: watchdog@e6020000 {
compatible = "renesas,r8a77965-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@ -2378,6 +2379,22 @@ sdhi3: mmc@ee160000 {
status = "disabled";
};
rpc: spi@ee200000 {
compatible = "renesas,r8a77965-rpc-if",
"renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x200>,
<0 0x08000000 0 0x04000000>,
<0 0xee208000 0 0x100>;
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
sata: sata@ee300000 {
compatible = "renesas,sata-r8a77965",
"renesas,rcar-gen3-sata";

1
arch/arm64/boot/dts/renesas/r8a77970.dtsi
View file

@ -108,6 +108,7 @@ rwdt: watchdog@e6020000 {
compatible = "renesas,r8a77970-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 402>;

1
arch/arm64/boot/dts/renesas/r8a77980.dtsi
View file

@ -138,6 +138,7 @@ rwdt: watchdog@e6020000 {
compatible = "renesas,r8a77980-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 402>;

17
arch/arm64/boot/dts/renesas/r8a77990.dtsi
View file

@ -171,6 +171,7 @@ rwdt: watchdog@e6020000 {
compatible = "renesas,r8a77990-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@ -1837,6 +1838,22 @@ sdhi3: mmc@ee160000 {
status = "disabled";
};
rpc: spi@ee200000 {
compatible = "renesas,r8a77990-rpc-if",
"renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x200>,
<0 0x08000000 0 0x04000000>,
<0 0xee208000 0 0x100>;
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;

17
arch/arm64/boot/dts/renesas/r8a77995.dtsi
View file

@ -94,6 +94,7 @@ rwdt: watchdog@e6020000 {
compatible = "renesas,r8a77995-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@ -1237,6 +1238,22 @@ sdhi2: mmc@ee140000 {
status = "disabled";
};
rpc: spi@ee200000 {
compatible = "renesas,r8a77995-rpc-if",
"renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x200>,
<0 0x08000000 0 0x04000000>,
<0 0xee208000 0 0x100>;
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;

12
arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
View file

@ -192,14 +192,17 @@ &i2c1 {
clock-frequency = <400000>;
bridge@2c {
pinctrl-0 = <&irq0_pins>;
pinctrl-names = "default";
compatible = "ti,sn65dsi86";
reg = <0x2c>;
clocks = <&sn65dsi86_refclk>;
clock-names = "refclk";
interrupt-parent = <&gpio1>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc_ex>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
vccio-supply = <&reg_1p8v>;
vpll-supply = <&reg_1p8v>;
@ -271,6 +274,11 @@ i2c6_pins: i2c6 {
function = "i2c6";
};
irq0_pins: irq0 {
groups = "intc_ex_irq0";
function = "intc_ex";
};
keys_pins: keys {
pins = "GP_6_18", "GP_6_19", "GP_6_20";
bias-pull-up;

24
arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
View file

@ -37,6 +37,20 @@ phy0: ethernet-phy@0 {
};
};
&canfd {
pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
};
channel1 {
status = "okay";
};
};
&i2c0 {
eeprom@51 {
compatible = "rohm,br24g01", "atmel,24c01";
@ -65,4 +79,14 @@ pins_mii {
};
};
canfd0_pins: canfd0 {
groups = "canfd0_data";
function = "canfd0";
};
canfd1_pins: canfd1 {
groups = "canfd1_data";
function = "canfd1";
};
};

57
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
View file

@ -24,6 +24,13 @@ aliases {
i2c6 = &i2c6;
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -81,6 +88,7 @@ rwdt: watchdog@e6020000 {
compatible = "renesas,r8a779a0-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 907>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 907>;
@ -596,6 +604,55 @@ hscif3: serial@e66a0000 {
status = "disabled";
};
canfd: can@e6660000 {
compatible = "renesas,r8a779a0-canfd";
reg = <0 0xe6660000 0 0x8000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 328>,
<&cpg CPG_CORE R8A779A0_CLK_CANFD>,
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A779A0_CLK_CANFD>;
assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 328>;
status = "disabled";
channel0 {
status = "disabled";
};
channel1 {
status = "disabled";
};
channel2 {
status = "disabled";
};
channel3 {
status = "disabled";
};
channel4 {
status = "disabled";
};
channel5 {
status = "disabled";
};
channel6 {
status = "disabled";
};
channel7 {
status = "disabled";
};
};
avb0: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen3";

20
arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
View file

@ -31,10 +31,30 @@ &extalr_clk {
clock-frequency = <32768>;
};
&i2c4 {
pinctrl-0 = <&i2c4_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
eeprom@50 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "cpu-board";
reg = <0x50>;
pagesize = <8>;
};
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
i2c4_pins: i2c4 {
groups = "i2c4";
function = "i2c4";
};
scif3_pins: scif3 {
groups = "scif3_data", "scif3_ctrl";
function = "scif3";

15
arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi Normal file
View file

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Spider Ethernet sub-board
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
&i2c4 {
eeprom@52 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "ethernet-sub-board";
reg = <0x52>;
pagesize = <8>;
};
};

10
arch/arm64/boot/dts/renesas/r8a779f0-spider.dts
View file

@ -7,6 +7,7 @@
/dts-v1/;
#include "r8a779f0-spider-cpu.dtsi"
#include "r8a779f0-spider-ethernet.dtsi"
/ {
model = "Renesas Spider CPU and Breakout boards based on r8a779f0";
@ -20,3 +21,12 @@ chosen {
stdout-path = "serial0:115200n8";
};
};
&i2c4 {
eeprom@51 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "breakout-board";
reg = <0x51>;
pagesize = <8>;
};
};

163
arch/arm64/boot/dts/renesas/r8a779f0.dtsi
View file

@ -63,6 +63,7 @@ rwdt: watchdog@e6020000 {
compatible = "renesas,r8a779f0-wdt",
"renesas,rcar-gen4-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 907>;
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 907>;
@ -75,6 +76,66 @@ pfc: pinctrl@e6050000 {
<0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>;
};
gpio0: gpio@e6050180 {
compatible = "renesas,gpio-r8a779f0",
"renesas,rcar-gen4-gpio";
reg = <0 0xe6050180 0 0x54>;
interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 915>;
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 915>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 0 21>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@e6050980 {
compatible = "renesas,gpio-r8a779f0",
"renesas,rcar-gen4-gpio";
reg = <0 0xe6050980 0 0x54>;
interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 915>;
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 915>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 32 25>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@e6051180 {
compatible = "renesas,gpio-r8a779f0",
"renesas,rcar-gen4-gpio";
reg = <0 0xe6051180 0 0x54>;
interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 915>;
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 915>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 64 17>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@e6051980 {
compatible = "renesas,gpio-r8a779f0",
"renesas,rcar-gen4-gpio";
reg = <0 0xe6051980 0 0x54>;
interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 915>;
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 915>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 96 19>;
interrupt-controller;
#interrupt-cells = <2>;
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a779f0-cpg-mssr";
reg = <0 0xe6150000 0 0x4000>;
@ -96,6 +157,108 @@ sysc: system-controller@e6180000 {
#power-domain-cells = <1>;
};
i2c0: i2c@e6500000 {
compatible = "renesas,i2c-r8a779f0",
"renesas,rcar-gen4-i2c";
reg = <0 0xe6500000 0 0x40>;
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 518>;
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 518>;
dmas = <&dmac0 0x91>, <&dmac0 0x90>,
<&dmac1 0x91>, <&dmac1 0x90>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@e6508000 {
compatible = "renesas,i2c-r8a779f0",
"renesas,rcar-gen4-i2c";
reg = <0 0xe6508000 0 0x40>;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 519>;
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 519>;
dmas = <&dmac0 0x93>, <&dmac0 0x92>,
<&dmac1 0x93>, <&dmac1 0x92>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@e6510000 {
compatible = "renesas,i2c-r8a779f0",
"renesas,rcar-gen4-i2c";
reg = <0 0xe6510000 0 0x40>;
interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 520>;
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 520>;
dmas = <&dmac0 0x95>, <&dmac0 0x94>,
<&dmac1 0x95>, <&dmac1 0x94>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@e66d0000 {
compatible = "renesas,i2c-r8a779f0",
"renesas,rcar-gen4-i2c";
reg = <0 0xe66d0000 0 0x40>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 521>;
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 521>;
dmas = <&dmac0 0x97>, <&dmac0 0x96>,
<&dmac1 0x97>, <&dmac1 0x96>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@e66d8000 {
compatible = "renesas,i2c-r8a779f0",
"renesas,rcar-gen4-i2c";
reg = <0 0xe66d8000 0 0x40>;
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 522>;
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 522>;
dmas = <&dmac0 0x99>, <&dmac0 0x98>,
<&dmac1 0x99>, <&dmac1 0x98>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@e66e0000 {
compatible = "renesas,i2c-r8a779f0",
"renesas,rcar-gen4-i2c";
reg = <0 0xe66e0000 0 0x40>;
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 523>;
dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
<&dmac1 0x9b>, <&dmac1 0x9a>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
scif3: serial@e6c50000 {
compatible = "renesas,scif-r8a779f0",
"renesas,rcar-gen4-scif", "renesas,scif";

481
arch/arm64/boot/dts/renesas/r9a07g043.dtsi Normal file
View file

@ -0,0 +1,481 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2UL SoC
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a07g043-cpg.h>
/ {
compatible = "renesas,r9a07g043";
#address-cells = <2>;
#size-cells = <2>;
audio_clk1: audio-clk1 {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by boards that provide it */
clock-frequency = <0>;
};
audio_clk2: audio-clk2 {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by boards that provide it */
clock-frequency = <0>;
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
extal_clk: extal-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
};
L3_CA55: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-size = <0x40000>;
};
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
ssi0: ssi@10049c00 {
reg = <0 0x10049c00 0 0x400>;
#sound-dai-cells = <0>;
/* place holder */
};
spi1: spi@1004b000 {
reg = <0 0x1004b000 0 0x400>;
#address-cells = <1>;
#size-cells = <0>;
/* place holder */
};
scif0: serial@1004b800 {
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004b800 0 0x400>;
interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
status = "disabled";
};
scif1: serial@1004bc00 {
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004bc00 0 0x400>;
interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>;
status = "disabled";
};
scif2: serial@1004c000 {
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004c000 0 0x400>;
interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>;
status = "disabled";
};
scif3: serial@1004c400 {
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004c400 0 0x400>;
interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>;
status = "disabled";
};
scif4: serial@1004c800 {
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004c800 0 0x400>;
interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>;
status = "disabled";
};
sci0: serial@1004d000 {
compatible = "renesas,r9a07g043-sci", "renesas,sci";
reg = <0 0x1004d000 0 0x400>;
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A07G043_SCI0_RST>;
status = "disabled";
};
sci1: serial@1004d400 {
compatible = "renesas,r9a07g043-sci", "renesas,sci";
reg = <0 0x1004d400 0 0x400>;
interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A07G043_SCI1_RST>;
status = "disabled";
};
canfd: can@10050000 {
reg = <0 0x10050000 0 0x8000>;
/* place holder */
};
i2c0: i2c@10058000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x10058000 0 0x400>;
/* place holder */
};
i2c1: i2c@10058400 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x10058400 0 0x400>;
/* place holder */
};
i2c3: i2c@10058c00 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x10058c00 0 0x400>;
/* place holder */
};
adc: adc@10059000 {
reg = <0 0x10059000 0 0x400>;
/* place holder */
};
sbc: spi@10060000 {
reg = <0 0x10060000 0 0x10000>,
<0 0x20000000 0 0x10000000>,
<0 0x10070000 0 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
/* place holder */
};
cpg: clock-controller@11010000 {
compatible = "renesas,r9a07g043-cpg";
reg = <0 0x11010000 0 0x10000>;
clocks = <&extal_clk>;
clock-names = "extal";
#clock-cells = <2>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
sysc: system-controller@11020000 {
compatible = "renesas,r9a07g043-sysc";
reg = <0 0x11020000 0 0x10000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "lpm_int", "ca55stbydone_int",
"cm33stbyr_int", "ca55_deny";
status = "disabled";
};
pinctrl: pinctrl@11030000 {
compatible = "renesas,r9a07g043-pinctrl";
reg = <0 0x11030000 0 0x10000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 152>;
clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
power-domains = <&cpg>;
resets = <&cpg R9A07G043_GPIO_RSTN>,
<&cpg R9A07G043_GPIO_PORT_RESETN>,
<&cpg R9A07G043_GPIO_SPARE_RESETN>;
};
dmac: dma-controller@11820000 {
compatible = "renesas,r9a07g043-dmac",
"renesas,rz-dmac";
reg = <0 0x11820000 0 0x10000>,
<0 0x11830000 0 0x10000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>,
<&cpg CPG_MOD R9A07G043_DMAC_PCLK>;
power-domains = <&cpg>;
resets = <&cpg R9A07G043_DMAC_ARESETN>,
<&cpg R9A07G043_DMAC_RST_ASYNC>;
#dma-cells = <1>;
dma-channels = <16>;
};
gic: interrupt-controller@11900000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0x11900000 0 0x40000>,
<0x0 0x11940000 0 0x60000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
sdhi0: mmc@11c00000 {
compatible = "renesas,sdhi-r9a07g043",
"renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c00000 0 0x10000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>,
<&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>,
<&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>,
<&cpg CPG_MOD R9A07G043_SDHI0_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg R9A07G043_SDHI0_IXRST>;
power-domains = <&cpg>;
status = "disabled";
};
sdhi1: mmc@11c10000 {
compatible = "renesas,sdhi-r9a07g043",
"renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c10000 0 0x10000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>,
<&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>,
<&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>,
<&cpg CPG_MOD R9A07G043_SDHI1_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg R9A07G043_SDHI1_IXRST>;
power-domains = <&cpg>;
status = "disabled";
};
eth0: ethernet@11c20000 {
compatible = "renesas,r9a07g043-gbeth",
"renesas,rzg2l-gbeth";
reg = <0 0x11c20000 0 0x10000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mux", "fil", "arp_ns";
phy-mode = "rgmii";
clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>,
<&cpg CPG_MOD R9A07G043_ETH0_CLK_CHI>,
<&cpg CPG_CORE R9A07G043_CLK_HP>;
clock-names = "axi", "chi", "refclk";
resets = <&cpg R9A07G043_ETH0_RST_HW_N>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
eth1: ethernet@11c30000 {
compatible = "renesas,r9a07g043-gbeth",
"renesas,rzg2l-gbeth";
reg = <0 0x11c30000 0 0x10000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mux", "fil", "arp_ns";
phy-mode = "rgmii";
clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>,
<&cpg CPG_MOD R9A07G043_ETH1_CLK_CHI>,
<&cpg CPG_CORE R9A07G043_CLK_HP>;
clock-names = "axi", "chi", "refclk";
resets = <&cpg R9A07G043_ETH1_RST_HW_N>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
phyrst: usbphy-ctrl@11c40000 {
reg = <0 0x11c40000 0 0x10000>;
/* place holder */
};
ohci0: usb@11c50000 {
reg = <0 0x11c50000 0 0x100>;
/* place holder */
};
ohci1: usb@11c70000 {
reg = <0 0x11c70000 0 0x100>;
/* place holder */
};
ehci0: usb@11c50100 {
reg = <0 0x11c50100 0 0x100>;
/* place holder */
};
ehci1: usb@11c70100 {
reg = <0 0x11c70100 0 0x100>;
/* place holder */
};
usb2_phy0: usb-phy@11c50200 {
reg = <0 0x11c50200 0 0x700>;
/* place holder */
};
usb2_phy1: usb-phy@11c70200 {
reg = <0 0x11c70200 0 0x700>;
/* place holder */
};
hsusb: usb@11c60000 {
reg = <0 0x11c60000 0 0x10000>;
/* place holder */
};
wdt0: watchdog@12800800 {
reg = <0 0x12800800 0 0x400>;
/* place holder */
};
wdt2: watchdog@12800400 {
reg = <0 0x12800400 0 0x400>;
/* place holder */
};
ostm0: timer@12801000 {
reg = <0x0 0x12801000 0x0 0x400>;
/* place holder */
};
ostm1: timer@12801400 {
reg = <0x0 0x12801400 0x0 0x400>;
/* place holder */
};
ostm2: timer@12801800 {
reg = <0x0 0x12801800 0x0 0x400>;
/* place holder */
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
};

97
arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts Normal file
View file

@ -0,0 +1,97 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2UL Type-1 SMARC EVK board
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r9a07g043.dtsi"
#include "rzg2ul-smarc.dtsi"
/ {
model = "Renesas SMARC EVK based on r9a07g043u11";
compatible = "renesas,smarc-evk", "renesas,r9a07g043u11", "renesas,r9a07g043";
};
&canfd {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&ehci0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&ehci1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&hsusb {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&i2c0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&i2c1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
wm8978: codec@1a {
compatible = "wlf,wm8978";
#sound-dai-cells = <0>;
reg = <0x1a>;
};
};
&ohci0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&ohci1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&phyrst {
status = "disabled";
};
&spi1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&ssi0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&usb2_phy0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&usb2_phy1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};

76
arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
View file

@ -13,79 +13,3 @@ / {
model = "Renesas SMARC EVK based on r9a07g044c2";
compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044";
};
&ehci0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&ehci1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&hsusb {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&i2c0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&i2c1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&i2c3 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&ohci0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&ohci1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&phyrst {
status = "disabled";
};
&spi1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&ssi0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&usb2_phy0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&usb2_phy1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};

584
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
View file

@ -42,6 +42,33 @@ extal_clk: extal {
clock-frequency = <0>;
};
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp-150000000 {
opp-hz = /bits/ 64 <150000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <300000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <300000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <300000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <300000>;
opp-suspend;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -65,6 +92,7 @@ cpu0: cpu@0 {
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@100 {
@ -74,6 +102,7 @@ cpu1: cpu@100 {
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
operating-points-v2 = <&cluster0_opp>;
};
L3_CA55: cache-controller-0 {
@ -83,6 +112,50 @@ L3_CA55: cache-controller-0 {
};
};
gpu_opp_table: opp-table-1 {
compatible = "operating-points-v2";
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <1100000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1100000>;
};
opp-250000000 {
opp-hz = /bits/ 64 <250000000>;
opp-microvolt = <1100000>;
};
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <1100000>;
};
opp-125000000 {
opp-hz = /bits/ 64 <125000000>;
opp-microvolt = <1100000>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <1100000>;
};
opp-62500000 {
opp-hz = /bits/ 64 <62500000>;
opp-microvolt = <1100000>;
};
opp-50000000 {
opp-hz = /bits/ 64 <50000000>;
opp-microvolt = <1100000>;
};
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
@ -96,16 +169,135 @@ soc: soc {
ranges;
ssi0: ssi@10049c00 {
compatible = "renesas,r9a07g054-ssi",
"renesas,rz-ssi";
reg = <0 0x10049c00 0 0x400>;
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>,
<&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
resets = <&cpg R9A07G054_SSI0_RST_M2_REG>;
dmas = <&dmac 0x2655>, <&dmac 0x2656>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
#sound-dai-cells = <0>;
/* place holder */
status = "disabled";
};
ssi1: ssi@1004a000 {
compatible = "renesas,r9a07g054-ssi",
"renesas,rz-ssi";
reg = <0 0x1004a000 0 0x400>;
interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>,
<&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
resets = <&cpg R9A07G054_SSI1_RST_M2_REG>;
dmas = <&dmac 0x2659>, <&dmac 0x265a>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
#sound-dai-cells = <0>;
status = "disabled";
};
ssi2: ssi@1004a400 {
compatible = "renesas,r9a07g054-ssi",
"renesas,rz-ssi";
reg = <0 0x1004a400 0 0x400>;
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>,
<&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
resets = <&cpg R9A07G054_SSI2_RST_M2_REG>;
dmas = <&dmac 0x265f>;
dma-names = "rt";
power-domains = <&cpg>;
#sound-dai-cells = <0>;
status = "disabled";
};
ssi3: ssi@1004a800 {
compatible = "renesas,r9a07g054-ssi",
"renesas,rz-ssi";
reg = <0 0x1004a800 0 0x400>;
interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>,
<&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
resets = <&cpg R9A07G054_SSI3_RST_M2_REG>;
dmas = <&dmac 0x2661>, <&dmac 0x2662>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
#sound-dai-cells = <0>;
status = "disabled";
};
spi0: spi@1004ac00 {
compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
reg = <0 0x1004ac00 0 0x400>;
interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G054_RSPI0_CLKB>;
resets = <&cpg R9A07G054_RSPI0_RST>;
power-domains = <&cpg>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@1004b000 {
compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
reg = <0 0x1004b000 0 0x400>;
interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G054_RSPI1_CLKB>;
resets = <&cpg R9A07G054_RSPI1_RST>;
power-domains = <&cpg>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
/* place holder */
status = "disabled";
};
spi2: spi@1004b400 {
compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
reg = <0 0x1004b400 0 0x400>;
interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G054_RSPI2_CLKB>;
resets = <&cpg R9A07G054_RSPI2_RST>;
power-domains = <&cpg>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
scif0: serial@1004b800 {
@ -234,43 +426,194 @@ sci1: serial@1004d400 {
};
canfd: can@10050000 {
compatible = "renesas,r9a07g054-canfd", "renesas,rzg2l-canfd";
reg = <0 0x10050000 0 0x8000>;
/* place holder */
interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "g_err", "g_recc",
"ch0_err", "ch0_rec", "ch0_trx",
"ch1_err", "ch1_rec", "ch1_trx";
clocks = <&cpg CPG_MOD R9A07G054_CANFD_PCLK>,
<&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>,
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>;
assigned-clock-rates = <50000000>;
resets = <&cpg R9A07G054_CANFD_RSTP_N>,
<&cpg R9A07G054_CANFD_RSTC_N>;
reset-names = "rstp_n", "rstc_n";
power-domains = <&cpg>;
status = "disabled";
channel0 {
status = "disabled";
};
channel1 {
status = "disabled";
};
};
i2c0: i2c@10058000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
reg = <0 0x10058000 0 0x400>;
/* place holder */
interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>;
clock-frequency = <100000>;
resets = <&cpg R9A07G054_I2C0_MRST>;
power-domains = <&cpg>;
status = "disabled";
};
i2c1: i2c@10058400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
reg = <0 0x10058400 0 0x400>;
/* place holder */
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>;
clock-frequency = <100000>;
resets = <&cpg R9A07G054_I2C1_MRST>;
power-domains = <&cpg>;
status = "disabled";
};
i2c2: i2c@10058800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
reg = <0 0x10058800 0 0x400>;
interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>;
clock-frequency = <100000>;
resets = <&cpg R9A07G054_I2C2_MRST>;
power-domains = <&cpg>;
status = "disabled";
};
i2c3: i2c@10058c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
reg = <0 0x10058c00 0 0x400>;
/* place holder */
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>;
clock-frequency = <100000>;
resets = <&cpg R9A07G054_I2C3_MRST>;
power-domains = <&cpg>;
status = "disabled";
};
adc: adc@10059000 {
compatible = "renesas,r9a07g054-adc", "renesas,rzg2l-adc";
reg = <0 0x10059000 0 0x400>;
/* place holder */
interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G054_ADC_ADCLK>,
<&cpg CPG_MOD R9A07G054_ADC_PCLK>;
clock-names = "adclk", "pclk";
resets = <&cpg R9A07G054_ADC_PRESETN>,
<&cpg R9A07G054_ADC_ADRST_N>;
reset-names = "presetn", "adrst-n";
power-domains = <&cpg>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
};
channel@1 {
reg = <1>;
};
channel@2 {
reg = <2>;
};
channel@3 {
reg = <3>;
};
channel@4 {
reg = <4>;
};
channel@5 {
reg = <5>;
};
channel@6 {
reg = <6>;
};
channel@7 {
reg = <7>;
};
};
tsu: thermal@10059400 {
compatible = "renesas,r9a07g054-tsu",
"renesas,rzg2l-tsu";
reg = <0 0x10059400 0 0x400>;
clocks = <&cpg CPG_MOD R9A07G054_TSU_PCLK>;
resets = <&cpg R9A07G054_TSU_PRESETN>;
power-domains = <&cpg>;
#thermal-sensor-cells = <1>;
};
sbc: spi@10060000 {
compatible = "renesas,r9a07g054-rpc-if",
"renesas,rzg2l-rpc-if";
reg = <0 0x10060000 0 0x10000>,
<0 0x20000000 0 0x10000000>,
<0 0x10070000 0 0x10000>;
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>,
<&cpg CPG_MOD R9A07G054_SPI_CLK>;
resets = <&cpg R9A07G054_SPI_RST>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
/* place holder */
status = "disabled";
};
cpg: clock-controller@11010000 {
@ -346,8 +689,24 @@ dmac: dma-controller@11820000 {
};
gpu: gpu@11840000 {
compatible = "renesas,r9a07g054-mali",
"arm,mali-bifrost";
reg = <0x0 0x11840000 0x0 0x10000>;
/* place holder */
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "job", "mmu", "gpu", "event";
clocks = <&cpg CPG_MOD R9A07G054_GPU_CLK>,
<&cpg CPG_MOD R9A07G054_GPU_AXI_CLK>,
<&cpg CPG_MOD R9A07G054_GPU_ACE_CLK>;
clock-names = "gpu", "bus", "bus_ace";
power-domains = <&cpg>;
resets = <&cpg R9A07G054_GPU_RESETN>,
<&cpg R9A07G054_GPU_AXI_RESETN>,
<&cpg R9A07G054_GPU_ACE_RESETN>;
reset-names = "rst", "axi_rst", "ace_rst";
operating-points-v2 = <&gpu_opp_table>;
};
gic: interrupt-controller@11900000 {
@ -361,13 +720,35 @@ gic: interrupt-controller@11900000 {
};
sdhi0: mmc@11c00000 {
compatible = "renesas,sdhi-r9a07g054",
"renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c00000 0 0x10000>;
/* place holder */
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>,
<&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>,
<&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>,
<&cpg CPG_MOD R9A07G054_SDHI0_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg R9A07G054_SDHI0_IXRST>;
power-domains = <&cpg>;
status = "disabled";
};
sdhi1: mmc@11c10000 {
compatible = "renesas,sdhi-r9a07g054",
"renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c10000 0 0x10000>;
/* place holder */
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>,
<&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>,
<&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>,
<&cpg CPG_MOD R9A07G054_SDHI1_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg R9A07G054_SDHI1_IXRST>;
power-domains = <&cpg>;
status = "disabled";
};
eth0: ethernet@11c20000 {
@ -411,73 +792,226 @@ eth1: ethernet@11c30000 {
};
phyrst: usbphy-ctrl@11c40000 {
compatible = "renesas,r9a07g054-usbphy-ctrl",
"renesas,rzg2l-usbphy-ctrl";
reg = <0 0x11c40000 0 0x10000>;
/* place holder */
clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>;
resets = <&cpg R9A07G054_USB_PRESETN>;
power-domains = <&cpg>;
#reset-cells = <1>;
status = "disabled";
};
ohci0: usb@11c50000 {
compatible = "generic-ohci";
reg = <0 0x11c50000 0 0x100>;
/* place holder */
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
<&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
resets = <&phyrst 0>,
<&cpg R9A07G054_USB_U2H0_HRESETN>;
phys = <&usb2_phy0 1>;
phy-names = "usb";
power-domains = <&cpg>;
status = "disabled";
};
ohci1: usb@11c70000 {
compatible = "generic-ohci";
reg = <0 0x11c70000 0 0x100>;
/* place holder */
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
<&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
resets = <&phyrst 1>,
<&cpg R9A07G054_USB_U2H1_HRESETN>;
phys = <&usb2_phy1 1>;
phy-names = "usb";
power-domains = <&cpg>;
status = "disabled";
};
ehci0: usb@11c50100 {
compatible = "generic-ehci";
reg = <0 0x11c50100 0 0x100>;
/* place holder */
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
<&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
resets = <&phyrst 0>,
<&cpg R9A07G054_USB_U2H0_HRESETN>;
phys = <&usb2_phy0 2>;
phy-names = "usb";
companion = <&ohci0>;
power-domains = <&cpg>;
status = "disabled";
};
ehci1: usb@11c70100 {
compatible = "generic-ehci";
reg = <0 0x11c70100 0 0x100>;
/* place holder */
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
<&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
resets = <&phyrst 1>,
<&cpg R9A07G054_USB_U2H1_HRESETN>;
phys = <&usb2_phy1 2>;
phy-names = "usb";
companion = <&ohci1>;
power-domains = <&cpg>;
status = "disabled";
};
usb2_phy0: usb-phy@11c50200 {
compatible = "renesas,usb2-phy-r9a07g054",
"renesas,rzg2l-usb2-phy";
reg = <0 0x11c50200 0 0x700>;
/* place holder */
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
<&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
resets = <&phyrst 0>;
#phy-cells = <1>;
power-domains = <&cpg>;
status = "disabled";
};
usb2_phy1: usb-phy@11c70200 {
compatible = "renesas,usb2-phy-r9a07g054",
"renesas,rzg2l-usb2-phy";
reg = <0 0x11c70200 0 0x700>;
/* place holder */
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
<&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
resets = <&phyrst 1>;
#phy-cells = <1>;
power-domains = <&cpg>;
status = "disabled";
};
hsusb: usb@11c60000 {
compatible = "renesas,usbhs-r9a07g054",
"renesas,rza2-usbhs";
reg = <0 0x11c60000 0 0x10000>;
/* place holder */
interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
<&cpg CPG_MOD R9A07G054_USB_U2P_EXR_CPUCLK>;
resets = <&phyrst 0>,
<&cpg R9A07G054_USB_U2P_EXL_SYSRST>;
renesas,buswait = <7>;
phys = <&usb2_phy0 3>;
phy-names = "usb";
power-domains = <&cpg>;
status = "disabled";
};
wdt0: watchdog@12800800 {
compatible = "renesas,r9a07g054-wdt",
"renesas,rzg2l-wdt";
reg = <0 0x12800800 0 0x400>;
/* place holder */
clocks = <&cpg CPG_MOD R9A07G054_WDT0_PCLK>,
<&cpg CPG_MOD R9A07G054_WDT0_CLK>;
clock-names = "pclk", "oscclk";
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A07G054_WDT0_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
wdt1: watchdog@12800c00 {
compatible = "renesas,r9a07g054-wdt",
"renesas,rzg2l-wdt";
reg = <0 0x12800C00 0 0x400>;
/* place holder */
clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>,
<&cpg CPG_MOD R9A07G054_WDT1_CLK>;
clock-names = "pclk", "oscclk";
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A07G054_WDT1_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
wdt2: watchdog@12800400 {
compatible = "renesas,r9a07g054-wdt",
"renesas,rzg2l-wdt";
reg = <0 0x12800400 0 0x400>;
/* place holder */
clocks = <&cpg CPG_MOD R9A07G054_WDT2_PCLK>,
<&cpg CPG_MOD R9A07G054_WDT2_CLK>;
clock-names = "pclk", "oscclk";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A07G054_WDT2_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
ostm0: timer@12801000 {
compatible = "renesas,r9a07g054-ostm",
"renesas,ostm";
reg = <0x0 0x12801000 0x0 0x400>;
/* place holder */
interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>;
resets = <&cpg R9A07G054_OSTM0_PRESETZ>;
power-domains = <&cpg>;
status = "disabled";
};
ostm1: timer@12801400 {
compatible = "renesas,r9a07g054-ostm",
"renesas,ostm";
reg = <0x0 0x12801400 0x0 0x400>;
/* place holder */
interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>;
resets = <&cpg R9A07G054_OSTM1_PRESETZ>;
power-domains = <&cpg>;
status = "disabled";
};
ostm2: timer@12801800 {
compatible = "renesas,r9a07g054-ostm",
"renesas,ostm";
reg = <0x0 0x12801800 0x0 0x400>;
/* place holder */
interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>;
resets = <&cpg R9A07G054_OSTM2_PRESETZ>;
power-domains = <&cpg>;
status = "disabled";
};
};
thermal-zones {
cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsu 0>;
sustainable-power = <717>;
cooling-maps {
map0 {
trip = <&target>;
cooling-device = <&cpu0 0 2>;
contribution = <1024>;
};
};
trips {
sensor_crit: sensor-crit {
temperature = <125000>;
hysteresis = <1000>;
type = "critical";
};
target: trip-point {
temperature = <100000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};

8
arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
View file

@ -16,11 +16,3 @@ / {
model = "Renesas SMARC EVK based on r9a07g054l2";
compatible = "renesas,smarc-evk", "renesas,r9a07g054l2", "renesas,r9a07g054";
};
&pinctrl {
/delete-node/ can0-stb-hog;
/delete-node/ can1-stb-hog;
/delete-node/ gpio-sd0-pwr-en-hog;
/delete-node/ sd0-dev-sel-hog;
/delete-node/ sd1-pwr-en-hog;
};

16
arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi
View file

@ -26,7 +26,6 @@ aliases {
serial0 = &scif0;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c3 = &i2c3;
};
chosen {
@ -75,7 +74,6 @@ vccq_sdhi1: regulator-vccq-sdhi1 {
regulator-name = "SDHI1 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1>, <1800000 0>;
};
@ -131,20 +129,6 @@ &i2c1 {
status = "okay";
};
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
clock-frequency = <400000>;
status = "okay";
wm8978: codec@1a {
compatible = "wlf,wm8978";
#sound-dai-cells = <0>;
reg = <0x1a>;
};
};
&ohci0 {
dr_mode = "otg";
status = "okay";

19
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
View file

@ -14,6 +14,21 @@
/ {
aliases {
serial1 = &scif2;
i2c3 = &i2c3;
};
};
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
clock-frequency = <400000>;
status = "okay";
wm8978: codec@1a {
compatible = "wlf,wm8978";
#sound-dai-cells = <0>;
reg = <0x1a>;
};
};
@ -33,3 +48,7 @@ &scif2 {
status = "okay";
};
#endif
&vccq_sdhi1 {
gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
};

64
arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
View file

@ -12,11 +12,6 @@ &pinctrl {
pinctrl-0 = <&sound_clk_pins>;
pinctrl-names = "default";
scif0_pins: scif0 {
pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
};
#if SW_SCIF_CAN
/* SW8 should be at position 2->1 */
can1_pins: can1 {
@ -25,13 +20,6 @@ can1_pins: can1 {
};
#endif
scif1_pins: scif1 {
pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */
<RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */
<RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */
};
#if SW_RSPI_CAN
/* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
can1-stb-hog {
@ -47,6 +35,33 @@ can1_pins: can1 {
};
#endif
i2c0_pins: i2c0 {
pins = "RIIC0_SDA", "RIIC0_SCL";
input-enable;
};
i2c1_pins: i2c1 {
pins = "RIIC1_SDA", "RIIC1_SCL";
input-enable;
};
i2c2_pins: i2c2 {
pinmux = <RZG2L_PORT_PINMUX(42, 3, 1)>, /* SDA */
<RZG2L_PORT_PINMUX(42, 4, 1)>; /* SCL */
};
scif0_pins: scif0 {
pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
};
scif1_pins: scif1 {
pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */
<RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */
<RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */
};
sd1-pwr-en-hog {
gpio-hog;
gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
@ -90,5 +105,30 @@ sound_clk_pins: sound_clk {
pins = "AUDIO_CLK1", "AUDIO_CLK2";
input-enable;
};
spi1_pins: spi1 {
pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
<RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
<RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
<RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
};
ssi0_pins: ssi0 {
pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
<RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
<RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */
<RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */
};
usb0_pins: usb0 {
pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */
<RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */
<RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */
};
usb1_pins: usb1 {
pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */
<RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */
};
};

61
arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
View file

@ -41,6 +41,15 @@ reg_3p3v: regulator1 {
regulator-always-on;
};
reg_1p1v: regulator-vdd-core {
compatible = "regulator-fixed";
regulator-name = "fixed-1.1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
@ -84,6 +93,18 @@ &extal_clk {
clock-frequency = <24000000>;
};
&gpu {
mali-supply = <&reg_1p1v>;
};
&ostm1 {
status = "okay";
};
&ostm2 {
status = "okay";
};
&pinctrl {
eth0_pins: eth0 {
pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
@ -110,6 +131,18 @@ gpio-sd0-pwr-en-hog {
line-name = "gpio_sd0_pwr_en";
};
qspi0_pins: qspi0 {
qspi0-data {
pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
power-source = <1800>;
};
qspi0-ctrl {
pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
power-source = <1800>;
};
};
/*
* SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
* The below switch logic can be used to select the device between
@ -175,6 +208,34 @@ sd0_mux_uhs {
};
};
&sbc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "micron,mt25qu512a", "jedec,spi-nor";
reg = <0>;
m25p,fast-read;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot@0 {
reg = <0x00000000 0x2000000>;
read-only;
};
user@2000000 {
reg = <0x2000000 0x2000000>;
};
};
};
};
#if (!SW_SD0_DEV_SEL)
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;

27
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
View file

@ -43,6 +43,7 @@
/ {
aliases {
serial1 = &scif1;
i2c2 = &i2c2;
};
};
@ -59,6 +60,20 @@ &canfd {
};
#endif
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
clock-frequency = <400000>;
status = "okay";
wm8978: codec@1a {
compatible = "wlf,wm8978";
#sound-dai-cells = <0>;
reg = <0x1a>;
};
};
/*
* To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
* SW1 should be at position 2->3 so that SER0_CTS# line is activated
@ -75,3 +90,15 @@ &scif1 {
status = "okay";
};
#endif
#if (SW_RSPI_CAN)
&spi1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
#endif
&vccq_sdhi1 {
gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
};

63
arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi Normal file
View file

@ -0,0 +1,63 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2UL SMARC pincontrol parts
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
&pinctrl {
pinctrl-0 = <&sound_clk_pins>;
pinctrl-names = "default";
scif0_pins: scif0 {
pinmux = <RZG2L_PORT_PINMUX(6, 4, 6)>, /* TxD */
<RZG2L_PORT_PINMUX(6, 3, 6)>; /* RxD */
};
sd1-pwr-en-hog {
gpio-hog;
gpios = <RZG2L_GPIO(0, 3) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "sd1_pwr_en";
};
sdhi1_pins: sd1 {
sd1_data {
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
power-source = <3300>;
};
sd1_ctrl {
pins = "SD1_CLK", "SD1_CMD";
power-source = <3300>;
};
sd1_mux {
pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
};
};
sdhi1_pins_uhs: sd1_uhs {
sd1_data_uhs {
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
power-source = <1800>;
};
sd1_ctrl_uhs {
pins = "SD1_CLK", "SD1_CMD";
power-source = <1800>;
};
sd1_mux_uhs {
pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
};
};
sound_clk_pins: sound_clk {
pins = "AUDIO_CLK1", "AUDIO_CLK2";
input-enable;
};
};

233
arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi Normal file
View file

@ -0,0 +1,233 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2UL SMARC SOM common parts
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/ {
aliases {
ethernet0 = &eth0;
ethernet1 = &eth1;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
#if !(SW_SW0_DEV_SEL)
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
states = <3300000 1>, <1800000 0>;
regulator-boot-on;
gpios = <&pinctrl RZG2L_GPIO(6, 2) GPIO_ACTIVE_HIGH>;
regulator-always-on;
};
#endif
};
#if (!SW_ET0_EN_N)
&eth0 {
pinctrl-0 = <&eth0_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
phy0: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <7>;
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
txdv-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
rxd3-skew-psec = <0>;
txd0-skew-psec = <0>;
txd1-skew-psec = <0>;
txd2-skew-psec = <0>;
txd3-skew-psec = <0>;
};
};
#endif
&eth1 {
pinctrl-0 = <&eth1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
status = "okay";
phy1: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <7>;
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
txdv-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
rxd3-skew-psec = <0>;
txd0-skew-psec = <0>;
txd1-skew-psec = <0>;
txd2-skew-psec = <0>;
txd3-skew-psec = <0>;
};
};
&extal_clk {
clock-frequency = <24000000>;
};
&pinctrl {
eth0_pins: eth0 {
pinmux = <RZG2L_PORT_PINMUX(4, 5, 1)>, /* ET0_LINKSTA */
<RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */
<RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */
<RZG2L_PORT_PINMUX(1, 0, 1)>, /* ET0_TXC */
<RZG2L_PORT_PINMUX(1, 1, 1)>, /* ET0_TX_CTL */
<RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */
<RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */
<RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */
<RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */
<RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */
<RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */
<RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
<RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
<RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
<RZG2L_PORT_PINMUX(4, 1, 1)>; /* ET0_RXD3 */
};
eth1_pins: eth1 {
pinmux = <RZG2L_PORT_PINMUX(10, 4, 1)>, /* ET1_LINKSTA */
<RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */
<RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */
<RZG2L_PORT_PINMUX(7, 0, 1)>, /* ET1_TXC */
<RZG2L_PORT_PINMUX(7, 1, 1)>, /* ET1_TX_CTL */
<RZG2L_PORT_PINMUX(7, 2, 1)>, /* ET1_TXD0 */
<RZG2L_PORT_PINMUX(7, 3, 1)>, /* ET1_TXD1 */
<RZG2L_PORT_PINMUX(7, 4, 1)>, /* ET1_TXD2 */
<RZG2L_PORT_PINMUX(8, 0, 1)>, /* ET1_TXD3 */
<RZG2L_PORT_PINMUX(8, 4, 1)>, /* ET1_RXC */
<RZG2L_PORT_PINMUX(9, 0, 1)>, /* ET1_RX_CTL */
<RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
<RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
<RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
<RZG2L_PORT_PINMUX(10, 0, 1)>; /* ET1_RXD3 */
};
sdhi0_emmc_pins: sd0emmc {
sd0_emmc_data {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
"SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
power-source = <1800>;
};
sd0_emmc_ctrl {
pins = "SD0_CLK", "SD0_CMD";
power-source = <1800>;
};
sd0_emmc_rst {
pins = "SD0_RST#";
power-source = <1800>;
};
};
sdhi0_pins: sd0 {
sd0_data {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
power-source = <3300>;
};
sd0_ctrl {
pins = "SD0_CLK", "SD0_CMD";
power-source = <3300>;
};
sd0_mux {
pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
};
};
sdhi0_pins_uhs: sd0_uhs {
sd0_data_uhs {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
power-source = <1800>;
};
sd0_ctrl_uhs {
pins = "SD0_CLK", "SD0_CMD";
power-source = <1800>;
};
sd0_mux_uhs {
pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
};
};
};
#if (SW_SW0_DEV_SEL)
&sdhi0 {
pinctrl-0 = <&sdhi0_emmc_pins>;
pinctrl-1 = <&sdhi0_emmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
non-removable;
fixed-emmc-driver-type = <1>;
status = "okay";
};
#else
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&vccq_sdhi0>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
#endif

24
arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi Normal file
View file

@ -0,0 +1,24 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2UL Type-1 SMARC EVK parts
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
/*
* DIP-Switch SW1 setting
* 1 : High; 0: Low
* SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
* SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
* Please change below macros according to SW1 setting
*/
#define SW_SW0_DEV_SEL 1
#define SW_ET0_EN_N 1
#include "rzg2ul-smarc-som.dtsi"
#include "rzg2ul-smarc-pinfunction.dtsi"
#include "rz-smarc-common.dtsi"
&vccq_sdhi1 {
gpios = <&pinctrl RZG2L_GPIO(6, 1) GPIO_ACTIVE_HIGH>;
};

49
arch/arm64/boot/dts/renesas/salvator-common.dtsi
View file

@ -866,6 +866,55 @@ rsnd_endpoint2: endpoint {
};
};
&rpc {
/* Left disabled. To be enabled by firmware when unlocked. */
flash@0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
bl2@40000 {
reg = <0x00040000 0x140000>;
read-only;
};
cert_header_sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x040000>;
read-only;
};
tee@200000 {
reg = <0x00200000 0x440000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x100000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";

49
arch/arm64/boot/dts/renesas/ulcb.dtsi
View file

@ -426,6 +426,55 @@ rsnd_for_hdmi: endpoint {
};
};
&rpc {
/* Left disabled. To be enabled by firmware when unlocked. */
flash@0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
bl2@40000 {
reg = <0x00040000 0x140000>;
read-only;
};
cert_header_sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x040000>;
read-only;
};
tee@200000 {
reg = <0x00200000 0x440000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x100000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";

184
include/dt-bindings/clock/r9a07g043-cpg.h Normal file
View file

@ -0,0 +1,184 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__
#define __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* R9A07G043 CPG Core Clocks */
#define R9A07G043_CLK_I 0
#define R9A07G043_CLK_I2 1
#define R9A07G043_CLK_S0 2
#define R9A07G043_CLK_SPI0 3
#define R9A07G043_CLK_SPI1 4
#define R9A07G043_CLK_SD0 5
#define R9A07G043_CLK_SD1 6
#define R9A07G043_CLK_M0 7
#define R9A07G043_CLK_M2 8
#define R9A07G043_CLK_M3 9
#define R9A07G043_CLK_HP 10
#define R9A07G043_CLK_TSU 11
#define R9A07G043_CLK_ZT 12
#define R9A07G043_CLK_P0 13
#define R9A07G043_CLK_P1 14
#define R9A07G043_CLK_P2 15
#define R9A07G043_CLK_AT 16
#define R9A07G043_OSCCLK 17
#define R9A07G043_CLK_P0_DIV2 18
/* R9A07G043 Module Clocks */
#define R9A07G043_CA55_SCLK 0 /* RZ/G2UL Only */
#define R9A07G043_CA55_PCLK 1 /* RZ/G2UL Only */
#define R9A07G043_CA55_ATCLK 2 /* RZ/G2UL Only */
#define R9A07G043_CA55_GICCLK 3 /* RZ/G2UL Only */
#define R9A07G043_CA55_PERICLK 4 /* RZ/G2UL Only */
#define R9A07G043_CA55_ACLK 5 /* RZ/G2UL Only */
#define R9A07G043_CA55_TSCLK 6 /* RZ/G2UL Only */
#define R9A07G043_GIC600_GICCLK 7 /* RZ/G2UL Only */
#define R9A07G043_IA55_CLK 8 /* RZ/G2UL Only */
#define R9A07G043_IA55_PCLK 9 /* RZ/G2UL Only */
#define R9A07G043_MHU_PCLK 10 /* RZ/G2UL Only */
#define R9A07G043_SYC_CNT_CLK 11
#define R9A07G043_DMAC_ACLK 12
#define R9A07G043_DMAC_PCLK 13
#define R9A07G043_OSTM0_PCLK 14
#define R9A07G043_OSTM1_PCLK 15
#define R9A07G043_OSTM2_PCLK 16
#define R9A07G043_MTU_X_MCK_MTU3 17
#define R9A07G043_POE3_CLKM_POE 18
#define R9A07G043_WDT0_PCLK 19
#define R9A07G043_WDT0_CLK 20
#define R9A07G043_WDT2_PCLK 21 /* RZ/G2UL Only */
#define R9A07G043_WDT2_CLK 22 /* RZ/G2UL Only */
#define R9A07G043_SPI_CLK2 23
#define R9A07G043_SPI_CLK 24
#define R9A07G043_SDHI0_IMCLK 25
#define R9A07G043_SDHI0_IMCLK2 26
#define R9A07G043_SDHI0_CLK_HS 27
#define R9A07G043_SDHI0_ACLK 28
#define R9A07G043_SDHI1_IMCLK 29
#define R9A07G043_SDHI1_IMCLK2 30
#define R9A07G043_SDHI1_CLK_HS 31
#define R9A07G043_SDHI1_ACLK 32
#define R9A07G043_ISU_ACLK 33 /* RZ/G2UL Only */
#define R9A07G043_ISU_PCLK 34 /* RZ/G2UL Only */
#define R9A07G043_CRU_SYSCLK 35 /* RZ/G2UL Only */
#define R9A07G043_CRU_VCLK 36 /* RZ/G2UL Only */
#define R9A07G043_CRU_PCLK 37 /* RZ/G2UL Only */
#define R9A07G043_CRU_ACLK 38 /* RZ/G2UL Only */
#define R9A07G043_LCDC_CLK_A 39 /* RZ/G2UL Only */
#define R9A07G043_LCDC_CLK_P 40 /* RZ/G2UL Only */
#define R9A07G043_LCDC_CLK_D 41 /* RZ/G2UL Only */
#define R9A07G043_SSI0_PCLK2 42
#define R9A07G043_SSI0_PCLK_SFR 43
#define R9A07G043_SSI1_PCLK2 44
#define R9A07G043_SSI1_PCLK_SFR 45
#define R9A07G043_SSI2_PCLK2 46
#define R9A07G043_SSI2_PCLK_SFR 47
#define R9A07G043_SSI3_PCLK2 48
#define R9A07G043_SSI3_PCLK_SFR 49
#define R9A07G043_SRC_CLKP 50 /* RZ/G2UL Only */
#define R9A07G043_USB_U2H0_HCLK 51
#define R9A07G043_USB_U2H1_HCLK 52
#define R9A07G043_USB_U2P_EXR_CPUCLK 53
#define R9A07G043_USB_PCLK 54
#define R9A07G043_ETH0_CLK_AXI 55
#define R9A07G043_ETH0_CLK_CHI 56
#define R9A07G043_ETH1_CLK_AXI 57
#define R9A07G043_ETH1_CLK_CHI 58
#define R9A07G043_I2C0_PCLK 59
#define R9A07G043_I2C1_PCLK 60
#define R9A07G043_I2C2_PCLK 61
#define R9A07G043_I2C3_PCLK 62
#define R9A07G043_SCIF0_CLK_PCK 63
#define R9A07G043_SCIF1_CLK_PCK 64
#define R9A07G043_SCIF2_CLK_PCK 65
#define R9A07G043_SCIF3_CLK_PCK 66
#define R9A07G043_SCIF4_CLK_PCK 67
#define R9A07G043_SCI0_CLKP 68
#define R9A07G043_SCI1_CLKP 69
#define R9A07G043_IRDA_CLKP 70
#define R9A07G043_RSPI0_CLKB 71
#define R9A07G043_RSPI1_CLKB 72
#define R9A07G043_RSPI2_CLKB 73
#define R9A07G043_CANFD_PCLK 74
#define R9A07G043_GPIO_HCLK 75
#define R9A07G043_ADC_ADCLK 76
#define R9A07G043_ADC_PCLK 77
#define R9A07G043_TSU_PCLK 78
/* R9A07G043 Resets */
#define R9A07G043_CA55_RST_1_0 0 /* RZ/G2UL Only */
#define R9A07G043_CA55_RST_1_1 1 /* RZ/G2UL Only */
#define R9A07G043_CA55_RST_3_0 2 /* RZ/G2UL Only */
#define R9A07G043_CA55_RST_3_1 3 /* RZ/G2UL Only */
#define R9A07G043_CA55_RST_4 4 /* RZ/G2UL Only */
#define R9A07G043_CA55_RST_5 5 /* RZ/G2UL Only */
#define R9A07G043_CA55_RST_6 6 /* RZ/G2UL Only */
#define R9A07G043_CA55_RST_7 7 /* RZ/G2UL Only */
#define R9A07G043_CA55_RST_8 8 /* RZ/G2UL Only */
#define R9A07G043_CA55_RST_9 9 /* RZ/G2UL Only */
#define R9A07G043_CA55_RST_10 10 /* RZ/G2UL Only */
#define R9A07G043_CA55_RST_11 11 /* RZ/G2UL Only */
#define R9A07G043_CA55_RST_12 12 /* RZ/G2UL Only */
#define R9A07G043_GIC600_GICRESET_N 13 /* RZ/G2UL Only */
#define R9A07G043_GIC600_DBG_GICRESET_N 14 /* RZ/G2UL Only */
#define R9A07G043_IA55_RESETN 15 /* RZ/G2UL Only */
#define R9A07G043_MHU_RESETN 16 /* RZ/G2UL Only */
#define R9A07G043_DMAC_ARESETN 17
#define R9A07G043_DMAC_RST_ASYNC 18
#define R9A07G043_SYC_RESETN 19
#define R9A07G043_OSTM0_PRESETZ 20
#define R9A07G043_OSTM1_PRESETZ 21
#define R9A07G043_OSTM2_PRESETZ 22
#define R9A07G043_MTU_X_PRESET_MTU3 23
#define R9A07G043_POE3_RST_M_REG 24
#define R9A07G043_WDT0_PRESETN 25
#define R9A07G043_WDT2_PRESETN 26 /* RZ/G2UL Only */
#define R9A07G043_SPI_RST 27
#define R9A07G043_SDHI0_IXRST 28
#define R9A07G043_SDHI1_IXRST 29
#define R9A07G043_ISU_ARESETN 30 /* RZ/G2UL Only */
#define R9A07G043_ISU_PRESETN 31 /* RZ/G2UL Only */
#define R9A07G043_CRU_CMN_RSTB 32 /* RZ/G2UL Only */
#define R9A07G043_CRU_PRESETN 33 /* RZ/G2UL Only */
#define R9A07G043_CRU_ARESETN 34 /* RZ/G2UL Only */
#define R9A07G043_LCDC_RESET_N 35 /* RZ/G2UL Only */
#define R9A07G043_SSI0_RST_M2_REG 36
#define R9A07G043_SSI1_RST_M2_REG 37
#define R9A07G043_SSI2_RST_M2_REG 38
#define R9A07G043_SSI3_RST_M2_REG 39
#define R9A07G043_SRC_RST 40 /* RZ/G2UL Only */
#define R9A07G043_USB_U2H0_HRESETN 41
#define R9A07G043_USB_U2H1_HRESETN 42
#define R9A07G043_USB_U2P_EXL_SYSRST 43
#define R9A07G043_USB_PRESETN 44
#define R9A07G043_ETH0_RST_HW_N 45
#define R9A07G043_ETH1_RST_HW_N 46
#define R9A07G043_I2C0_MRST 47
#define R9A07G043_I2C1_MRST 48
#define R9A07G043_I2C2_MRST 49
#define R9A07G043_I2C3_MRST 50
#define R9A07G043_SCIF0_RST_SYSTEM_N 51
#define R9A07G043_SCIF1_RST_SYSTEM_N 52
#define R9A07G043_SCIF2_RST_SYSTEM_N 53
#define R9A07G043_SCIF3_RST_SYSTEM_N 54
#define R9A07G043_SCIF4_RST_SYSTEM_N 55
#define R9A07G043_SCI0_RST 56
#define R9A07G043_SCI1_RST 57
#define R9A07G043_IRDA_RST 58
#define R9A07G043_RSPI0_RST 59
#define R9A07G043_RSPI1_RST 60
#define R9A07G043_RSPI2_RST 61
#define R9A07G043_CANFD_RSTP_N 62
#define R9A07G043_CANFD_RSTC_N 63
#define R9A07G043_GPIO_RSTN 64
#define R9A07G043_GPIO_PORT_RESETN 65
#define R9A07G043_GPIO_SPARE_RESETN 66
#define R9A07G043_ADC_PRESETN 67
#define R9A07G043_ADC_ADRST_N 68
#define R9A07G043_TSU_PRESETN 69
#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */