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https://github.com/torvalds/linux
synced 2024-10-04 02:10:58 +00:00
ndtest: Add regions and mappings to the test buses
The bus config array is used to hold the regions and the respective mappings. This config based interface enables to change the dimm/region/namespace layouts easily. Signed-off-by: Santosh Sivaraj <santosh@fossix.org> Link: https://lore.kernel.org/r/20201222042240.2983755-6-santosh@fossix.org Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Santosh Sivaraj
Dan Williams
parent
5e41396f72
commit
6fde2d4c8b
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@ -23,6 +23,7 @@ enum {
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LABEL_SIZE = SZ_128K,
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NUM_INSTANCES = 2,
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NUM_DCR = 4,
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NDTEST_MAX_MAPPING = 6,
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};
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#define NDTEST_SCM_DIMM_CMD_MASK \
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@ -88,18 +89,161 @@ static struct ndtest_dimm dimm_group2[] = {
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},
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};
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static struct ndtest_mapping region0_mapping[] = {
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{
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.dimm = 0,
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.position = 0,
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.start = 0,
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.size = SZ_16M,
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},
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{
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.dimm = 1,
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.position = 1,
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.start = 0,
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.size = SZ_16M,
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}
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};
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static struct ndtest_mapping region1_mapping[] = {
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{
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.dimm = 0,
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.position = 0,
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.start = SZ_16M,
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.size = SZ_16M,
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},
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{
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.dimm = 1,
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.position = 1,
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.start = SZ_16M,
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.size = SZ_16M,
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},
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{
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.dimm = 2,
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.position = 2,
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.start = SZ_16M,
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.size = SZ_16M,
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},
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{
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.dimm = 3,
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.position = 3,
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.start = SZ_16M,
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.size = SZ_16M,
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},
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};
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static struct ndtest_mapping region2_mapping[] = {
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{
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.dimm = 0,
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.position = 0,
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.start = 0,
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.size = DIMM_SIZE,
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},
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};
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static struct ndtest_mapping region3_mapping[] = {
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{
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.dimm = 1,
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.start = 0,
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.size = DIMM_SIZE,
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}
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};
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static struct ndtest_mapping region4_mapping[] = {
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{
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.dimm = 2,
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.start = 0,
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.size = DIMM_SIZE,
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}
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};
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static struct ndtest_mapping region5_mapping[] = {
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{
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.dimm = 3,
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.start = 0,
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.size = DIMM_SIZE,
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}
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};
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static struct ndtest_region bus0_regions[] = {
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{
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.type = ND_DEVICE_NAMESPACE_PMEM,
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.num_mappings = ARRAY_SIZE(region0_mapping),
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.mapping = region0_mapping,
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.size = DIMM_SIZE,
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.range_index = 1,
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},
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{
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.type = ND_DEVICE_NAMESPACE_PMEM,
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.num_mappings = ARRAY_SIZE(region1_mapping),
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.mapping = region1_mapping,
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.size = DIMM_SIZE * 2,
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.range_index = 2,
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},
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{
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.type = ND_DEVICE_NAMESPACE_BLK,
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.num_mappings = ARRAY_SIZE(region2_mapping),
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.mapping = region2_mapping,
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.size = DIMM_SIZE,
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.range_index = 3,
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},
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{
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.type = ND_DEVICE_NAMESPACE_BLK,
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.num_mappings = ARRAY_SIZE(region3_mapping),
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.mapping = region3_mapping,
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.size = DIMM_SIZE,
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.range_index = 4,
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},
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{
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.type = ND_DEVICE_NAMESPACE_BLK,
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.num_mappings = ARRAY_SIZE(region4_mapping),
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.mapping = region4_mapping,
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.size = DIMM_SIZE,
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.range_index = 5,
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},
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{
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.type = ND_DEVICE_NAMESPACE_BLK,
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.num_mappings = ARRAY_SIZE(region5_mapping),
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.mapping = region5_mapping,
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.size = DIMM_SIZE,
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.range_index = 6,
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},
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};
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static struct ndtest_mapping region6_mapping[] = {
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{
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.dimm = 0,
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.position = 0,
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.start = 0,
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.size = DIMM_SIZE,
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},
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};
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static struct ndtest_region bus1_regions[] = {
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{
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.type = ND_DEVICE_NAMESPACE_IO,
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.num_mappings = ARRAY_SIZE(region6_mapping),
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.mapping = region6_mapping,
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.size = DIMM_SIZE,
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.range_index = 1,
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},
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};
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static struct ndtest_config bus_configs[NUM_INSTANCES] = {
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/* bus 1 */
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{
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.dimm_start = 0,
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.dimm_count = ARRAY_SIZE(dimm_group1),
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.dimms = dimm_group1,
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.regions = bus0_regions,
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.num_regions = ARRAY_SIZE(bus0_regions),
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},
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/* bus 2 */
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{
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.dimm_start = ARRAY_SIZE(dimm_group1),
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.dimm_count = ARRAY_SIZE(dimm_group2),
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.dimms = dimm_group2,
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.regions = bus1_regions,
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.num_regions = ARRAY_SIZE(bus1_regions),
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},
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};
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@ -140,6 +284,95 @@ static int ndtest_ctl(struct nvdimm_bus_descriptor *nd_desc,
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return 0;
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}
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static int ndtest_blk_do_io(struct nd_blk_region *ndbr, resource_size_t dpa,
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void *iobuf, u64 len, int rw)
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{
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struct ndtest_dimm *dimm = ndbr->blk_provider_data;
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struct ndtest_blk_mmio *mmio = dimm->mmio;
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struct nd_region *nd_region = &ndbr->nd_region;
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unsigned int lane;
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if (!mmio)
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return -ENOMEM;
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lane = nd_region_acquire_lane(nd_region);
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if (rw)
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memcpy(mmio->base + dpa, iobuf, len);
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else {
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memcpy(iobuf, mmio->base + dpa, len);
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arch_invalidate_pmem(mmio->base + dpa, len);
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}
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nd_region_release_lane(nd_region, lane);
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return 0;
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}
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static int ndtest_blk_region_enable(struct nvdimm_bus *nvdimm_bus,
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struct device *dev)
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{
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struct nd_blk_region *ndbr = to_nd_blk_region(dev);
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struct nvdimm *nvdimm;
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struct ndtest_dimm *dimm;
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struct ndtest_blk_mmio *mmio;
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nvdimm = nd_blk_region_to_dimm(ndbr);
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dimm = nvdimm_provider_data(nvdimm);
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nd_blk_region_set_provider_data(ndbr, dimm);
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dimm->blk_region = to_nd_region(dev);
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mmio = devm_kzalloc(dev, sizeof(struct ndtest_blk_mmio), GFP_KERNEL);
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if (!mmio)
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return -ENOMEM;
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mmio->base = (void __iomem *) devm_nvdimm_memremap(
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dev, dimm->address, 12, nd_blk_memremap_flags(ndbr));
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if (!mmio->base) {
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dev_err(dev, "%s failed to map blk dimm\n", nvdimm_name(nvdimm));
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return -ENOMEM;
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}
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mmio->size = dimm->size;
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mmio->base_offset = 0;
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dimm->mmio = mmio;
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return 0;
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}
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static struct nfit_test_resource *ndtest_resource_lookup(resource_size_t addr)
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{
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int i;
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for (i = 0; i < NUM_INSTANCES; i++) {
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struct nfit_test_resource *n, *nfit_res = NULL;
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struct ndtest_priv *t = instances[i];
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if (!t)
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continue;
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spin_lock(&ndtest_lock);
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list_for_each_entry(n, &t->resources, list) {
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if (addr >= n->res.start && (addr < n->res.start
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+ resource_size(&n->res))) {
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nfit_res = n;
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break;
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} else if (addr >= (unsigned long) n->buf
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&& (addr < (unsigned long) n->buf
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+ resource_size(&n->res))) {
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nfit_res = n;
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break;
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}
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}
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spin_unlock(&ndtest_lock);
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if (nfit_res)
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return nfit_res;
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}
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pr_warn("Failed to get resource\n");
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return NULL;
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}
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static void ndtest_release_resource(void *data)
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{
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struct nfit_test_resource *res = data;
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@ -207,6 +440,119 @@ static void *ndtest_alloc_resource(struct ndtest_priv *p, size_t size,
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return NULL;
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}
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static ssize_t range_index_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct nd_region *nd_region = to_nd_region(dev);
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struct ndtest_region *region = nd_region_provider_data(nd_region);
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return sprintf(buf, "%d\n", region->range_index);
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}
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static DEVICE_ATTR_RO(range_index);
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static struct attribute *ndtest_region_attributes[] = {
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&dev_attr_range_index.attr,
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NULL,
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};
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static const struct attribute_group ndtest_region_attribute_group = {
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.name = "papr",
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.attrs = ndtest_region_attributes,
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};
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static const struct attribute_group *ndtest_region_attribute_groups[] = {
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&ndtest_region_attribute_group,
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NULL,
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};
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static int ndtest_create_region(struct ndtest_priv *p,
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struct ndtest_region *region)
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{
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struct nd_mapping_desc mappings[NDTEST_MAX_MAPPING];
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struct nd_blk_region_desc ndbr_desc;
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struct nd_interleave_set *nd_set;
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struct nd_region_desc *ndr_desc;
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struct resource res;
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int i, ndimm = region->mapping[0].dimm;
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u64 uuid[2];
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memset(&res, 0, sizeof(res));
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memset(&mappings, 0, sizeof(mappings));
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memset(&ndbr_desc, 0, sizeof(ndbr_desc));
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ndr_desc = &ndbr_desc.ndr_desc;
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if (!ndtest_alloc_resource(p, region->size, &res.start))
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return -ENOMEM;
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res.end = res.start + region->size - 1;
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ndr_desc->mapping = mappings;
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ndr_desc->res = &res;
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ndr_desc->provider_data = region;
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ndr_desc->attr_groups = ndtest_region_attribute_groups;
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if (uuid_parse(p->config->dimms[ndimm].uuid_str, (uuid_t *)uuid)) {
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pr_err("failed to parse UUID\n");
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return -ENXIO;
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}
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nd_set = devm_kzalloc(&p->pdev.dev, sizeof(*nd_set), GFP_KERNEL);
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if (!nd_set)
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return -ENOMEM;
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nd_set->cookie1 = cpu_to_le64(uuid[0]);
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nd_set->cookie2 = cpu_to_le64(uuid[1]);
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nd_set->altcookie = nd_set->cookie1;
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ndr_desc->nd_set = nd_set;
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if (region->type == ND_DEVICE_NAMESPACE_BLK) {
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mappings[0].start = 0;
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mappings[0].size = DIMM_SIZE;
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mappings[0].nvdimm = p->config->dimms[ndimm].nvdimm;
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ndr_desc->mapping = &mappings[0];
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ndr_desc->num_mappings = 1;
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ndr_desc->num_lanes = 1;
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ndbr_desc.enable = ndtest_blk_region_enable;
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ndbr_desc.do_io = ndtest_blk_do_io;
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region->region = nvdimm_blk_region_create(p->bus, ndr_desc);
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goto done;
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}
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for (i = 0; i < region->num_mappings; i++) {
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ndimm = region->mapping[i].dimm;
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mappings[i].start = region->mapping[i].start;
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mappings[i].size = region->mapping[i].size;
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mappings[i].position = region->mapping[i].position;
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mappings[i].nvdimm = p->config->dimms[ndimm].nvdimm;
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}
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ndr_desc->num_mappings = region->num_mappings;
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region->region = nvdimm_pmem_region_create(p->bus, ndr_desc);
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done:
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if (!region->region) {
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dev_err(&p->pdev.dev, "Error registering region %pR\n",
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ndr_desc->res);
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return -ENXIO;
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}
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return 0;
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}
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static int ndtest_init_regions(struct ndtest_priv *p)
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{
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int i, ret = 0;
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for (i = 0; i < p->config->num_regions; i++) {
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ret = ndtest_create_region(p, &p->config->regions[i]);
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if (ret)
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return ret;
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}
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return 0;
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}
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static void put_dimms(void *data)
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{
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struct ndtest_priv *p = data;
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@ -552,6 +898,10 @@ static int ndtest_probe(struct platform_device *pdev)
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if (rc)
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goto err;
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rc = ndtest_init_regions(p);
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if (rc)
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goto err;
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rc = devm_add_action_or_reset(&pdev->dev, put_dimms, p);
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if (rc)
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goto err;
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@ -617,6 +967,8 @@ static __init int ndtest_init(void)
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dax_pmem_compat_test();
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#endif
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nfit_test_setup(ndtest_resource_lookup, NULL);
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ndtest_dimm_class = class_create(THIS_MODULE, "nfit_test_dimm");
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if (IS_ERR(ndtest_dimm_class)) {
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rc = PTR_ERR(ndtest_dimm_class);
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@ -20,6 +20,15 @@ struct ndtest_priv {
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dma_addr_t *dimm_dma;
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};
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struct ndtest_blk_mmio {
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void __iomem *base;
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u64 size;
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u64 base_offset;
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u32 line_size;
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u32 num_lines;
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u32 table_size;
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};
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struct ndtest_dimm {
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struct device *dev;
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struct nvdimm *nvdimm;
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@ -42,8 +51,25 @@ struct ndtest_dimm {
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u8 no_alias;
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};
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struct ndtest_mapping {
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u64 start;
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u64 size;
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u8 position;
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u8 dimm;
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};
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struct ndtest_region {
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struct nd_region *region;
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struct ndtest_mapping *mapping;
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u64 size;
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u8 type;
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u8 num_mappings;
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u8 range_index;
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};
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struct ndtest_config {
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struct ndtest_dimm *dimms;
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struct ndtest_region *regions;
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unsigned int dimm_count;
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unsigned int dimm_start;
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u8 num_regions;
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