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Merge series "ASoC: ti: j721e-evm: Support for j7200 variant" from Peter Ujfalusi <peter.ujfalusi@ti.com>:
Hi, Changes since v1: - Suffix the 2359296000 constant with 'u' to silence C90 warning When j7200 SOM is connected to the CPB, the audio setup is a bit different: Only 48KHz family have clock path, 44.1KHz is not supported. Update the binding documentation and add support for the j7200 version of CPB to the driver. Regards, Peter --- Peter Ujfalusi (2): ASoC: dt-bindings: ti,j721e-cpb-audio: Document support for j7200-cpb ASoC: ti: j721e-evm: Add support for j7200-cpb audio .../bindings/sound/ti,j721e-cpb-audio.yaml | 92 ++++++++++++++----- sound/soc/ti/j721e-evm.c | 11 +++ 2 files changed, 81 insertions(+), 22 deletions(-) -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
This commit is contained in:
Mark Brown
commit
6ea8a79bf6
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@ -18,18 +18,25 @@ description: |
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PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
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different HSDIVIDER.
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Clocking setup for 48KHz family:
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PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
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|-> PLL4_HSDIV2 ---> AUDIO_REFCLK2 ---> pcm3168a.SCKI
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Clocking setup for j721e:
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48KHz family:
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PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
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|-> PLL4_HSDIV2 ---> AUDIO_REFCLK2 ---> pcm3168a.SCKI
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Clocking setup for 44.1KHz family:
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PLL15 ---> PLL15_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
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|-> PLL15_HSDIV2 ---> AUDIO_REFCLK2 ---> pcm3168a.SCKI
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44.1KHz family:
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PLL15 ---> PLL15_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
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|-> PLL15_HSDIV2 ---> AUDIO_REFCLK2 ---> pcm3168a.SCKI
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Clocking setup for j7200:
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48KHz family:
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PLL4 ---> PLL4_HSDIV0 ---> MCASP0_AUXCLK ---> McASP0.auxclk
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|-> PLL4_HSDIV2 ---> AUDIO_REFCLK2 ---> pcm3168a.SCKI
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properties:
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compatible:
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items:
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- const: ti,j721e-cpb-audio
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enum:
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- ti,j721e-cpb-audio
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- ti,j7200-cpb-audio
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model:
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$ref: /schemas/types.yaml#/definitions/string
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@ -44,22 +51,12 @@ properties:
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$ref: /schemas/types.yaml#/definitions/phandle
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clocks:
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items:
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- description: AUXCLK clock for McASP used by CPB audio
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- description: Parent for CPB_McASP auxclk (for 48KHz)
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- description: Parent for CPB_McASP auxclk (for 44.1KHz)
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- description: SCKI clock for the pcm3168a codec on CPB
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- description: Parent for CPB_SCKI clock (for 48KHz)
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- description: Parent for CPB_SCKI clock (for 44.1KHz)
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minItems: 4
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maxItems: 6
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clock-names:
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items:
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- const: cpb-mcasp-auxclk
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- const: cpb-mcasp-auxclk-48000
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- const: cpb-mcasp-auxclk-44100
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- const: cpb-codec-scki
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- const: cpb-codec-scki-48000
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- const: cpb-codec-scki-44100
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minItems: 4
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maxItems: 6
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required:
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- compatible
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@ -71,6 +68,57 @@ required:
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: ti,j721e-cpb-audio
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then:
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properties:
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clocks:
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minItems: 6
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items:
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- description: AUXCLK clock for McASP used by CPB audio
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- description: Parent for CPB_McASP auxclk (for 48KHz)
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- description: Parent for CPB_McASP auxclk (for 44.1KHz)
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- description: SCKI clock for the pcm3168a codec on CPB
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- description: Parent for CPB_SCKI clock (for 48KHz)
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- description: Parent for CPB_SCKI clock (for 44.1KHz)
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clock-names:
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items:
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- const: cpb-mcasp-auxclk
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- const: cpb-mcasp-auxclk-48000
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- const: cpb-mcasp-auxclk-44100
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- const: cpb-codec-scki
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- const: cpb-codec-scki-48000
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- const: cpb-codec-scki-44100
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- if:
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properties:
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compatible:
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contains:
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const: ti,j7200-cpb-audio
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then:
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properties:
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clocks:
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maxItems: 4
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items:
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- description: AUXCLK clock for McASP used by CPB audio
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- description: Parent for CPB_McASP auxclk (for 48KHz)
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- description: SCKI clock for the pcm3168a codec on CPB
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- description: Parent for CPB_SCKI clock (for 48KHz)
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clock-names:
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items:
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- const: cpb-mcasp-auxclk
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- const: cpb-mcasp-auxclk-48000
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- const: cpb-codec-scki
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- const: cpb-codec-scki-48000
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examples:
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- |+
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sound {
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@ -525,6 +525,14 @@ static const struct j721e_audio_match_data j721e_cpb_ivi_data = {
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},
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};
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static const struct j721e_audio_match_data j7200_cpb_data = {
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.board_type = J721E_BOARD_CPB,
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.num_links = 2, /* CPB pcm3168a */
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.pll_rates = {
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[J721E_CLK_PARENT_48000] = 2359296000u, /* PLL4 */
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},
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};
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static const struct of_device_id j721e_audio_of_match[] = {
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{
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.compatible = "ti,j721e-cpb-audio",
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@ -532,6 +540,9 @@ static const struct of_device_id j721e_audio_of_match[] = {
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}, {
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.compatible = "ti,j721e-cpb-ivi-audio",
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.data = &j721e_cpb_ivi_data,
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}, {
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.compatible = "ti,j7200-cpb-audio",
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.data = &j7200_cpb_data,
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},
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{ },
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};
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