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ARM: EXYNOS: Migrate clock support to common clock framework
Remove Samsung specific clock support in Exynos4/5 and migrate to use common clock framework. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Thomas Abraham
Kukjin Kim
parent
f2585b1cce
commit
6e6aac7590
19 changed files with 10 additions and 3835 deletions
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@ -865,6 +865,7 @@ config ARCH_EXYNOS
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select ARCH_HAS_HOLES_MEMORYMODEL
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select ARCH_SPARSEMEM_ENABLE
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select CLKDEV_LOOKUP
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select COMMON_CLK
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select CPU_V7
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select GENERIC_CLOCKEVENTS
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select HAVE_CLK
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@ -13,10 +13,6 @@ obj- :=
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# Core
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obj-$(CONFIG_ARCH_EXYNOS) += common.o
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obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o
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obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
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obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
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obj-$(CONFIG_SOC_EXYNOS5250) += clock-exynos5.o
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obj-$(CONFIG_PM) += pm.o
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obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
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File diff suppressed because it is too large
Load diff
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@ -1,35 +0,0 @@
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/*
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* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Header file for exynos4 clock support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_CLOCK_H
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#define __ASM_ARCH_CLOCK_H __FILE__
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#include <linux/clk.h>
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extern struct clksrc_clk exynos4_clk_aclk_133;
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extern struct clksrc_clk exynos4_clk_mout_mpll;
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extern struct clksrc_sources exynos4_clkset_mout_corebus;
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extern struct clksrc_sources exynos4_clkset_group;
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extern struct clk *exynos4_clkset_aclk_top_list[];
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extern struct clk *exynos4_clkset_group_list[];
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extern struct clksrc_sources exynos4_clkset_mout_g2d0;
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extern struct clksrc_sources exynos4_clkset_mout_g2d1;
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extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
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extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
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extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
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extern int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable);
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extern int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable);
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#endif /* __ASM_ARCH_CLOCK_H */
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@ -1,187 +0,0 @@
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/*
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* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS4210 - Clock support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/syscore_ops.h>
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#include <plat/cpu-freq.h>
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#include <plat/clock.h>
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#include <plat/cpu.h>
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#include <plat/pll.h>
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#include <plat/s5p-clock.h>
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#include <plat/clock-clksrc.h>
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#include <plat/pm.h>
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include "common.h"
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#include "clock-exynos4.h"
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#ifdef CONFIG_PM_SLEEP
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static struct sleep_save exynos4210_clock_save[] = {
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SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
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SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
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SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
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SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
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SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
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SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
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SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
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SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
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};
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#endif
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static struct clksrc_clk *sysclks[] = {
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/* nothing here yet */
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};
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static struct clksrc_clk exynos4210_clk_mout_g2d0 = {
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.clk = {
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.name = "mout_g2d0",
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},
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.sources = &exynos4_clkset_mout_g2d0,
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.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
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};
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static struct clksrc_clk exynos4210_clk_mout_g2d1 = {
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.clk = {
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.name = "mout_g2d1",
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},
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.sources = &exynos4_clkset_mout_g2d1,
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.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
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};
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static struct clk *exynos4210_clkset_mout_g2d_list[] = {
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[0] = &exynos4210_clk_mout_g2d0.clk,
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[1] = &exynos4210_clk_mout_g2d1.clk,
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};
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static struct clksrc_sources exynos4210_clkset_mout_g2d = {
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.sources = exynos4210_clkset_mout_g2d_list,
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.nr_sources = ARRAY_SIZE(exynos4210_clkset_mout_g2d_list),
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};
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static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
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}
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static struct clksrc_clk clksrcs[] = {
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{
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.clk = {
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.name = "sclk_sata",
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.id = -1,
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.enable = exynos4_clksrc_mask_fsys_ctrl,
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.ctrlbit = (1 << 24),
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},
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.sources = &exynos4_clkset_mout_corebus,
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.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
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.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_fimd",
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.devname = "exynos4-fb.1",
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.enable = exynos4_clksrc_mask_lcd1_ctrl,
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.ctrlbit = (1 << 0),
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},
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.sources = &exynos4_clkset_group,
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.reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
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.reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_fimg2d",
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},
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.sources = &exynos4210_clkset_mout_g2d,
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.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
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.reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
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},
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};
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static struct clk init_clocks_off[] = {
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{
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.name = "sataphy",
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.id = -1,
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.parent = &exynos4_clk_aclk_133.clk,
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.enable = exynos4_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 3),
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}, {
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.name = "sata",
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.id = -1,
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.parent = &exynos4_clk_aclk_133.clk,
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.enable = exynos4_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 10),
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}, {
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.name = "fimd",
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.devname = "exynos4-fb.1",
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.enable = exynos4_clk_ip_lcd1_ctrl,
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.ctrlbit = (1 << 0),
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}, {
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.name = "sysmmu",
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.devname = "exynos-sysmmu.9",
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.enable = exynos4_clk_ip_image_ctrl,
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.ctrlbit = (1 << 3),
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}, {
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.name = "sysmmu",
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.devname = "exynos-sysmmu.11",
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.enable = exynos4_clk_ip_lcd1_ctrl,
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.ctrlbit = (1 << 4),
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}, {
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.name = "fimg2d",
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.enable = exynos4_clk_ip_image_ctrl,
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.ctrlbit = (1 << 0),
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},
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};
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#ifdef CONFIG_PM_SLEEP
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static int exynos4210_clock_suspend(void)
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{
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s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
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return 0;
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}
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static void exynos4210_clock_resume(void)
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{
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s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
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}
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#else
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#define exynos4210_clock_suspend NULL
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#define exynos4210_clock_resume NULL
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#endif
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static struct syscore_ops exynos4210_clock_syscore_ops = {
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.suspend = exynos4210_clock_suspend,
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.resume = exynos4210_clock_resume,
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};
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void __init exynos4210_register_clocks(void)
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{
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int ptr;
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exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
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exynos4_clk_mout_mpll.reg_src.shift = 8;
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exynos4_clk_mout_mpll.reg_src.size = 1;
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for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
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s3c_register_clksrc(sysclks[ptr], 1);
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s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
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s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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register_syscore_ops(&exynos4210_clock_syscore_ops);
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}
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@ -1,201 +0,0 @@
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/*
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* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS4212 - Clock support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/syscore_ops.h>
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#include <plat/cpu-freq.h>
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#include <plat/clock.h>
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#include <plat/cpu.h>
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#include <plat/pll.h>
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#include <plat/s5p-clock.h>
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#include <plat/clock-clksrc.h>
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#include <plat/pm.h>
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include "common.h"
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#include "clock-exynos4.h"
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#ifdef CONFIG_PM_SLEEP
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static struct sleep_save exynos4212_clock_save[] = {
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SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
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SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
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SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
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SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
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};
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#endif
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static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
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}
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static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
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}
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static struct clk *clk_src_mpll_user_list[] = {
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[0] = &clk_fin_mpll,
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[1] = &exynos4_clk_mout_mpll.clk,
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};
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static struct clksrc_sources clk_src_mpll_user = {
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.sources = clk_src_mpll_user_list,
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.nr_sources = ARRAY_SIZE(clk_src_mpll_user_list),
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};
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static struct clksrc_clk clk_mout_mpll_user = {
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.clk = {
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.name = "mout_mpll_user",
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},
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.sources = &clk_src_mpll_user,
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.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
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};
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static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
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.clk = {
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.name = "mout_g2d0",
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},
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.sources = &exynos4_clkset_mout_g2d0,
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.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
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};
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static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
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.clk = {
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.name = "mout_g2d1",
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},
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.sources = &exynos4_clkset_mout_g2d1,
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.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
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};
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static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
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[0] = &exynos4x12_clk_mout_g2d0.clk,
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[1] = &exynos4x12_clk_mout_g2d1.clk,
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};
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static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
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.sources = exynos4x12_clkset_mout_g2d_list,
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.nr_sources = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
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};
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static struct clksrc_clk *sysclks[] = {
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&clk_mout_mpll_user,
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};
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static struct clksrc_clk clksrcs[] = {
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{
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.clk = {
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.name = "sclk_fimg2d",
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},
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.sources = &exynos4x12_clkset_mout_g2d,
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.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },
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.reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },
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},
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};
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static struct clk init_clocks_off[] = {
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{
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.name = "sysmmu",
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.devname = "exynos-sysmmu.9",
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.enable = exynos4_clk_ip_dmc_ctrl,
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.ctrlbit = (1 << 24),
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}, {
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.name = "sysmmu",
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.devname = "exynos-sysmmu.12",
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.enable = exynos4212_clk_ip_isp0_ctrl,
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.ctrlbit = (7 << 8),
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}, {
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.name = "sysmmu",
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.devname = "exynos-sysmmu.13",
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.enable = exynos4212_clk_ip_isp1_ctrl,
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.ctrlbit = (1 << 4),
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}, {
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.name = "sysmmu",
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.devname = "exynos-sysmmu.14",
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.enable = exynos4212_clk_ip_isp0_ctrl,
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.ctrlbit = (1 << 11),
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}, {
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.name = "sysmmu",
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.devname = "exynos-sysmmu.15",
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.enable = exynos4212_clk_ip_isp0_ctrl,
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.ctrlbit = (1 << 12),
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}, {
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.name = "flite",
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.devname = "exynos-fimc-lite.0",
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.enable = exynos4212_clk_ip_isp0_ctrl,
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.ctrlbit = (1 << 4),
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}, {
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.name = "flite",
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.devname = "exynos-fimc-lite.1",
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.enable = exynos4212_clk_ip_isp0_ctrl,
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.ctrlbit = (1 << 3),
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}, {
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.name = "fimg2d",
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.enable = exynos4_clk_ip_dmc_ctrl,
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.ctrlbit = (1 << 23),
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},
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};
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#ifdef CONFIG_PM_SLEEP
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static int exynos4212_clock_suspend(void)
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{
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s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
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return 0;
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}
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static void exynos4212_clock_resume(void)
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{
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s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
|
||||
}
|
||||
|
||||
#else
|
||||
#define exynos4212_clock_suspend NULL
|
||||
#define exynos4212_clock_resume NULL
|
||||
#endif
|
||||
|
||||
static struct syscore_ops exynos4212_clock_syscore_ops = {
|
||||
.suspend = exynos4212_clock_suspend,
|
||||
.resume = exynos4212_clock_resume,
|
||||
};
|
||||
|
||||
void __init exynos4212_register_clocks(void)
|
||||
{
|
||||
int ptr;
|
||||
|
||||
/* usbphy1 is removed */
|
||||
exynos4_clkset_group_list[4] = NULL;
|
||||
|
||||
/* mout_mpll_user is used */
|
||||
exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
|
||||
exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
|
||||
|
||||
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
|
||||
exynos4_clk_mout_mpll.reg_src.shift = 12;
|
||||
exynos4_clk_mout_mpll.reg_src.size = 1;
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
|
||||
s3c_register_clksrc(sysclks[ptr], 1);
|
||||
|
||||
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
|
||||
|
||||
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
|
||||
register_syscore_ops(&exynos4212_clock_syscore_ops);
|
||||
}
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -39,7 +39,6 @@
|
|||
#include <mach/regs-gpio.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/pm.h>
|
||||
#include <plat/sdhci.h>
|
||||
|
|
@ -65,8 +64,6 @@ static const char name_exynos5440[] = "EXYNOS5440";
|
|||
static void exynos4_map_io(void);
|
||||
static void exynos5_map_io(void);
|
||||
static void exynos5440_map_io(void);
|
||||
static void exynos4_init_clocks(int xtal);
|
||||
static void exynos5_init_clocks(int xtal);
|
||||
static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
|
||||
static int exynos_init(void);
|
||||
|
||||
|
|
@ -75,7 +72,6 @@ static struct cpu_table cpu_ids[] __initdata = {
|
|||
.idcode = EXYNOS4210_CPU_ID,
|
||||
.idmask = EXYNOS4_CPU_MASK,
|
||||
.map_io = exynos4_map_io,
|
||||
.init_clocks = exynos4_init_clocks,
|
||||
.init_uarts = exynos4_init_uarts,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos4210,
|
||||
|
|
@ -83,7 +79,6 @@ static struct cpu_table cpu_ids[] __initdata = {
|
|||
.idcode = EXYNOS4212_CPU_ID,
|
||||
.idmask = EXYNOS4_CPU_MASK,
|
||||
.map_io = exynos4_map_io,
|
||||
.init_clocks = exynos4_init_clocks,
|
||||
.init_uarts = exynos4_init_uarts,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos4212,
|
||||
|
|
@ -91,7 +86,6 @@ static struct cpu_table cpu_ids[] __initdata = {
|
|||
.idcode = EXYNOS4412_CPU_ID,
|
||||
.idmask = EXYNOS4_CPU_MASK,
|
||||
.map_io = exynos4_map_io,
|
||||
.init_clocks = exynos4_init_clocks,
|
||||
.init_uarts = exynos4_init_uarts,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos4412,
|
||||
|
|
@ -99,7 +93,6 @@ static struct cpu_table cpu_ids[] __initdata = {
|
|||
.idcode = EXYNOS5250_SOC_ID,
|
||||
.idmask = EXYNOS5_SOC_MASK,
|
||||
.map_io = exynos5_map_io,
|
||||
.init_clocks = exynos5_init_clocks,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos5250,
|
||||
}, {
|
||||
|
|
@ -397,45 +390,11 @@ static void __init exynos5_map_io(void)
|
|||
iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
|
||||
}
|
||||
|
||||
static void __init exynos4_init_clocks(int xtal)
|
||||
{
|
||||
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
|
||||
|
||||
s3c24xx_register_baseclocks(xtal);
|
||||
s5p_register_clocks(xtal);
|
||||
|
||||
if (soc_is_exynos4210())
|
||||
exynos4210_register_clocks();
|
||||
else if (soc_is_exynos4212() || soc_is_exynos4412())
|
||||
exynos4212_register_clocks();
|
||||
|
||||
exynos4_register_clocks();
|
||||
exynos4_setup_clocks();
|
||||
}
|
||||
|
||||
static void __init exynos5440_map_io(void)
|
||||
{
|
||||
iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
|
||||
}
|
||||
|
||||
static void __init exynos5_init_clocks(int xtal)
|
||||
{
|
||||
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
|
||||
|
||||
/* EXYNOS5440 can support only common clock framework */
|
||||
|
||||
if (soc_is_exynos5440())
|
||||
return;
|
||||
|
||||
#ifdef CONFIG_SOC_EXYNOS5250
|
||||
s3c24xx_register_baseclocks(xtal);
|
||||
s5p_register_clocks(xtal);
|
||||
|
||||
exynos5_register_clocks();
|
||||
exynos5_setup_clocks();
|
||||
#endif
|
||||
}
|
||||
|
||||
void __init exynos4_init_irq(void)
|
||||
{
|
||||
unsigned int gic_bank_offset;
|
||||
|
|
|
|||
|
|
@ -12,7 +12,10 @@
|
|||
#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
|
||||
#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
|
||||
|
||||
#include <linux/of.h>
|
||||
|
||||
extern void mct_init(void);
|
||||
void exynos_init_time(void);
|
||||
|
||||
struct map_desc;
|
||||
void exynos_init_io(struct map_desc *mach_desc, int size);
|
||||
|
|
@ -22,6 +25,10 @@ void exynos4_restart(char mode, const char *cmd);
|
|||
void exynos5_restart(char mode, const char *cmd);
|
||||
void exynos_init_late(void);
|
||||
|
||||
/* ToDo: remove these after migrating legacy exynos4 platforms to dt */
|
||||
void exynos4_clk_init(struct device_node *np);
|
||||
void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
|
||||
|
||||
#ifdef CONFIG_PM_GENERIC_DOMAINS
|
||||
int exynos_pm_late_initcall(void);
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -256,113 +256,6 @@
|
|||
#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
|
||||
#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
|
||||
|
||||
/* For EXYNOS5250 */
|
||||
|
||||
#define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000)
|
||||
#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100)
|
||||
#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200)
|
||||
#define EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400)
|
||||
#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500)
|
||||
#define EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504)
|
||||
#define EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600)
|
||||
#define EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604)
|
||||
|
||||
#define EXYNOS5_PWR_CTRL1 EXYNOS_CLKREG(0x01020)
|
||||
#define EXYNOS5_PWR_CTRL2 EXYNOS_CLKREG(0x01024)
|
||||
|
||||
#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100)
|
||||
#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204)
|
||||
|
||||
#define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900)
|
||||
|
||||
#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500)
|
||||
|
||||
#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130)
|
||||
#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134)
|
||||
#define EXYNOS5_EPLL_CON2 EXYNOS_CLKREG(0x10138)
|
||||
#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140)
|
||||
#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144)
|
||||
#define EXYNOS5_VPLL_CON2 EXYNOS_CLKREG(0x10148)
|
||||
#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120)
|
||||
|
||||
#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210)
|
||||
#define EXYNOS5_CLKSRC_TOP1 EXYNOS_CLKREG(0x10214)
|
||||
#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
|
||||
#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C)
|
||||
#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220)
|
||||
#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
|
||||
#define EXYNOS5_CLKSRC_MAUDIO EXYNOS_CLKREG(0x10240)
|
||||
#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
|
||||
#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
|
||||
#define EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254)
|
||||
#define EXYNOS5_SCLK_SRC_ISP EXYNOS_CLKREG(0x10270)
|
||||
|
||||
#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
|
||||
#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
|
||||
#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)
|
||||
#define EXYNOS5_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x10334)
|
||||
#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)
|
||||
#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)
|
||||
#define EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354)
|
||||
|
||||
#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)
|
||||
#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)
|
||||
#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520)
|
||||
#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C)
|
||||
#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C)
|
||||
#define EXYNOS5_CLKDIV_MAUDIO EXYNOS_CLKREG(0x10544)
|
||||
#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548)
|
||||
#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C)
|
||||
#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
|
||||
#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
|
||||
#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
|
||||
#define EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C)
|
||||
#define EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560)
|
||||
#define EXYNOS5_CLKDIV_PERIC3 EXYNOS_CLKREG(0x10564)
|
||||
#define EXYNOS5_CLKDIV_PERIC4 EXYNOS_CLKREG(0x10568)
|
||||
#define EXYNOS5_CLKDIV_PERIC5 EXYNOS_CLKREG(0x1056C)
|
||||
#define EXYNOS5_SCLK_DIV_ISP EXYNOS_CLKREG(0x10580)
|
||||
|
||||
#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
|
||||
#define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800)
|
||||
#define EXYNOS5_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x0C804)
|
||||
#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
|
||||
#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)
|
||||
#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)
|
||||
#define EXYNOS5_CLKGATE_IP_G3D EXYNOS_CLKREG(0x10930)
|
||||
#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934)
|
||||
#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944)
|
||||
#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C)
|
||||
#define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950)
|
||||
#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960)
|
||||
#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980)
|
||||
|
||||
#define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110)
|
||||
#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)
|
||||
#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)
|
||||
|
||||
#define EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24)
|
||||
|
||||
#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)
|
||||
|
||||
#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)
|
||||
|
||||
#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
|
||||
#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
|
||||
#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
|
||||
#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
|
||||
#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
|
||||
#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
|
||||
#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
|
||||
#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
|
||||
|
||||
#define PWR_CTRL2_DIV2_UP_EN (1 << 25)
|
||||
#define PWR_CTRL2_DIV1_UP_EN (1 << 24)
|
||||
#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16)
|
||||
#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
|
||||
#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
|
||||
#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
|
||||
|
||||
/* Compatibility defines and inclusion */
|
||||
|
||||
#include <mach/regs-pmu.h>
|
||||
|
|
|
|||
|
|
@ -177,7 +177,6 @@ static void __init armlex4210_smsc911x_init(void)
|
|||
static void __init armlex4210_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(24000000);
|
||||
s3c24xx_init_uarts(armlex4210_uartcfgs,
|
||||
ARRAY_SIZE(armlex4210_uartcfgs));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -124,7 +124,6 @@ static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
|
|||
static void __init exynos4_dt_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(24000000);
|
||||
}
|
||||
|
||||
static void __init exynos4_dt_machine_init(void)
|
||||
|
|
|
|||
|
|
@ -152,12 +152,7 @@ static const struct of_dev_auxdata exynos5440_auxdata_lookup[] __initconst = {
|
|||
|
||||
static void __init exynos5_dt_map_io(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
|
||||
exynos_init_io(NULL, 0);
|
||||
|
||||
if (of_flat_dt_is_compatible(root, "samsung,exynos5250"))
|
||||
s3c24xx_init_clocks(24000000);
|
||||
}
|
||||
|
||||
static void __init exynos5_dt_machine_init(void)
|
||||
|
|
|
|||
|
|
@ -1330,7 +1330,6 @@ static struct platform_device *nuri_devices[] __initdata = {
|
|||
static void __init nuri_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(clk_xusbxti.rate);
|
||||
s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -754,7 +754,6 @@ static void s5p_tv_setup(void)
|
|||
static void __init origen_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(clk_xusbxti.rate);
|
||||
s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -322,7 +322,6 @@ static struct platform_device *smdk4x12_devices[] __initdata = {
|
|||
static void __init smdk4x12_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(clk_xusbxti.rate);
|
||||
s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -371,7 +371,6 @@ static void s5p_tv_setup(void)
|
|||
static void __init smdkv310_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(clk_xusbxti.rate);
|
||||
s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1092,7 +1092,6 @@ static struct platform_device *universal_devices[] __initdata = {
|
|||
static void __init universal_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(clk_xusbxti.rate);
|
||||
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ config PLAT_S5P
|
|||
select PLAT_SAMSUNG
|
||||
select S3C_GPIO_TRACK
|
||||
select S5P_GPIO_DRVSTR
|
||||
select SAMSUNG_CLKSRC
|
||||
select SAMSUNG_CLKSRC if !COMMON_CLK
|
||||
select SAMSUNG_GPIOLIB_4BIT
|
||||
select SAMSUNG_IRQ_VIC_TIMER
|
||||
help
|
||||
|
|
@ -89,7 +89,7 @@ config SAMSUNG_CLKSRC
|
|||
used by newer systems such as the S3C64XX.
|
||||
|
||||
config S5P_CLOCK
|
||||
def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
|
||||
def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
|
||||
help
|
||||
Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue