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mfd: Add support for the MediaTek MT6397 PMIC
This adds support for the MediaTek MT6397 PMIC. This is a multifunction device with the following sub modules: - Regulator - RTC - Audio codec - GPIO - Clock It is interfaced to the host controller using SPI interface by a proprietary hardware called PMIC wrapper or pwrap. MT6397 MFD is a child device of the pwrap. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Flora Fu
Lee Jones
parent
82a00c49ed
commit
6df8dd5c18
5 changed files with 664 additions and 0 deletions
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@ -503,6 +503,16 @@ config MFD_MAX8998
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additional drivers must be enabled in order to use the functionality
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of the device.
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config MFD_MT6397
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tristate "MediaTek MT6397 PMIC Support"
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select MFD_CORE
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select IRQ_DOMAIN
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help
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Say yes here to add support for MediaTek MT6397 PMIC. This is
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a Power Management IC. This driver provides common support for
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accessing the device; additional drivers must be enabled in order
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to use the functionality of the device.
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config MFD_MENF21BMC
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tristate "MEN 14F021P00 Board Management Controller Support"
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depends on I2C
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@ -181,3 +181,4 @@ obj-$(CONFIG_MFD_RT5033) += rt5033.o
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intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o
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obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
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obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
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227
drivers/mfd/mt6397-core.c
Normal file
227
drivers/mfd/mt6397-core.c
Normal file
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@ -0,0 +1,227 @@
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Flora Fu, MediaTek
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/regmap.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/mt6397/core.h>
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#include <linux/mfd/mt6397/registers.h>
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static const struct mfd_cell mt6397_devs[] = {
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{
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.name = "mt6397-rtc",
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.of_compatible = "mediatek,mt6397-rtc",
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}, {
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.name = "mt6397-regulator",
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.of_compatible = "mediatek,mt6397-regulator",
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}, {
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.name = "mt6397-codec",
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.of_compatible = "mediatek,mt6397-codec",
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}, {
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.name = "mt6397-clk",
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.of_compatible = "mediatek,mt6397-clk",
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},
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};
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static void mt6397_irq_lock(struct irq_data *data)
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{
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struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq);
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mutex_lock(&mt6397->irqlock);
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}
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static void mt6397_irq_sync_unlock(struct irq_data *data)
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{
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struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq);
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regmap_write(mt6397->regmap, MT6397_INT_CON0, mt6397->irq_masks_cur[0]);
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regmap_write(mt6397->regmap, MT6397_INT_CON1, mt6397->irq_masks_cur[1]);
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mutex_unlock(&mt6397->irqlock);
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}
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static void mt6397_irq_disable(struct irq_data *data)
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{
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struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq);
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int shift = data->hwirq & 0xf;
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int reg = data->hwirq >> 4;
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mt6397->irq_masks_cur[reg] &= ~BIT(shift);
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}
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static void mt6397_irq_enable(struct irq_data *data)
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{
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struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq);
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int shift = data->hwirq & 0xf;
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int reg = data->hwirq >> 4;
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mt6397->irq_masks_cur[reg] |= BIT(shift);
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}
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static struct irq_chip mt6397_irq_chip = {
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.name = "mt6397-irq",
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.irq_bus_lock = mt6397_irq_lock,
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.irq_bus_sync_unlock = mt6397_irq_sync_unlock,
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.irq_enable = mt6397_irq_enable,
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.irq_disable = mt6397_irq_disable,
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};
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static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
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int irqbase)
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{
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unsigned int status;
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int i, irq, ret;
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ret = regmap_read(mt6397->regmap, reg, &status);
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if (ret) {
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dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
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return;
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}
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for (i = 0; i < 16; i++) {
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if (status & BIT(i)) {
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irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
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if (irq)
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handle_nested_irq(irq);
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}
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}
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regmap_write(mt6397->regmap, reg, status);
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}
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static irqreturn_t mt6397_irq_thread(int irq, void *data)
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{
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struct mt6397_chip *mt6397 = data;
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mt6397_irq_handle_reg(mt6397, MT6397_INT_STATUS0, 0);
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mt6397_irq_handle_reg(mt6397, MT6397_INT_STATUS1, 16);
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return IRQ_HANDLED;
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}
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static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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struct mt6397_chip *mt6397 = d->host_data;
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irq_set_chip_data(irq, mt6397);
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irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
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irq_set_nested_thread(irq, 1);
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#ifdef CONFIG_ARM
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set_irq_flags(irq, IRQF_VALID);
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#else
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irq_set_noprobe(irq);
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#endif
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return 0;
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}
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static struct irq_domain_ops mt6397_irq_domain_ops = {
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.map = mt6397_irq_domain_map,
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};
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static int mt6397_irq_init(struct mt6397_chip *mt6397)
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{
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int ret;
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mutex_init(&mt6397->irqlock);
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/* Mask all interrupt sources */
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regmap_write(mt6397->regmap, MT6397_INT_CON0, 0x0);
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regmap_write(mt6397->regmap, MT6397_INT_CON1, 0x0);
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mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node,
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MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397);
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if (!mt6397->irq_domain) {
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dev_err(mt6397->dev, "could not create irq domain\n");
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return -ENOMEM;
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}
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ret = devm_request_threaded_irq(mt6397->dev, mt6397->irq, NULL,
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mt6397_irq_thread, IRQF_ONESHOT, "mt6397-pmic", mt6397);
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if (ret) {
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dev_err(mt6397->dev, "failed to register irq=%d; err: %d\n",
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mt6397->irq, ret);
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return ret;
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}
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return 0;
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}
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static int mt6397_probe(struct platform_device *pdev)
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{
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int ret;
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struct mt6397_chip *mt6397;
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mt6397 = devm_kzalloc(&pdev->dev, sizeof(*mt6397), GFP_KERNEL);
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if (!mt6397)
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return -ENOMEM;
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mt6397->dev = &pdev->dev;
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/*
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* mt6397 MFD is child device of soc pmic wrapper.
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* Regmap is set from its parent.
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*/
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mt6397->regmap = dev_get_regmap(pdev->dev.parent, NULL);
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if (!mt6397->regmap)
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return -ENODEV;
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platform_set_drvdata(pdev, mt6397);
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mt6397->irq = platform_get_irq(pdev, 0);
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if (mt6397->irq > 0) {
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ret = mt6397_irq_init(mt6397);
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if (ret)
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return ret;
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}
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ret = mfd_add_devices(&pdev->dev, -1, mt6397_devs,
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ARRAY_SIZE(mt6397_devs), NULL, 0, NULL);
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if (ret)
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dev_err(&pdev->dev, "failed to add child devices: %d\n", ret);
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return ret;
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}
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static int mt6397_remove(struct platform_device *pdev)
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{
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mfd_remove_devices(&pdev->dev);
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return 0;
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}
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static const struct of_device_id mt6397_of_match[] = {
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{ .compatible = "mediatek,mt6397" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, mt6397_of_match);
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static struct platform_driver mt6397_driver = {
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.probe = mt6397_probe,
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.remove = mt6397_remove,
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.driver = {
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.name = "mt6397",
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.of_match_table = of_match_ptr(mt6397_of_match),
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},
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};
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module_platform_driver(mt6397_driver);
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MODULE_AUTHOR("Flora Fu, MediaTek");
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MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:mt6397");
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64
include/linux/mfd/mt6397/core.h
Normal file
64
include/linux/mfd/mt6397/core.h
Normal file
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@ -0,0 +1,64 @@
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Flora Fu, MediaTek
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MFD_MT6397_CORE_H__
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#define __MFD_MT6397_CORE_H__
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enum mt6397_irq_numbers {
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MT6397_IRQ_SPKL_AB = 0,
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MT6397_IRQ_SPKR_AB,
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MT6397_IRQ_SPKL,
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MT6397_IRQ_SPKR,
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MT6397_IRQ_BAT_L,
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MT6397_IRQ_BAT_H,
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MT6397_IRQ_FG_BAT_L,
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MT6397_IRQ_FG_BAT_H,
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MT6397_IRQ_WATCHDOG,
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MT6397_IRQ_PWRKEY,
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MT6397_IRQ_THR_L,
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MT6397_IRQ_THR_H,
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MT6397_IRQ_VBATON_UNDET,
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MT6397_IRQ_BVALID_DET,
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MT6397_IRQ_CHRDET,
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MT6397_IRQ_OV,
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MT6397_IRQ_LDO,
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MT6397_IRQ_HOMEKEY,
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MT6397_IRQ_ACCDET,
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MT6397_IRQ_AUDIO,
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MT6397_IRQ_RTC,
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MT6397_IRQ_PWRKEY_RSTB,
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MT6397_IRQ_HDMI_SIFM,
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MT6397_IRQ_HDMI_CEC,
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MT6397_IRQ_VCA15,
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MT6397_IRQ_VSRMCA15,
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MT6397_IRQ_VCORE,
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MT6397_IRQ_VGPU,
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MT6397_IRQ_VIO18,
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MT6397_IRQ_VPCA7,
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MT6397_IRQ_VSRMCA7,
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MT6397_IRQ_VDRM,
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MT6397_IRQ_NR,
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};
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struct mt6397_chip {
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struct device *dev;
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struct regmap *regmap;
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int irq;
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struct irq_domain *irq_domain;
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struct mutex irqlock;
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u16 irq_masks_cur[2];
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u16 irq_masks_cache[2];
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};
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#endif /* __MFD_MT6397_CORE_H__ */
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362
include/linux/mfd/mt6397/registers.h
Normal file
362
include/linux/mfd/mt6397/registers.h
Normal file
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@ -0,0 +1,362 @@
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Flora Fu, MediaTek
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MFD_MT6397_REGISTERS_H__
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#define __MFD_MT6397_REGISTERS_H__
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/* PMIC Registers */
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#define MT6397_CID 0x0100
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#define MT6397_TOP_CKPDN 0x0102
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#define MT6397_TOP_CKPDN_SET 0x0104
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#define MT6397_TOP_CKPDN_CLR 0x0106
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#define MT6397_TOP_CKPDN2 0x0108
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#define MT6397_TOP_CKPDN2_SET 0x010A
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#define MT6397_TOP_CKPDN2_CLR 0x010C
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#define MT6397_TOP_GPIO_CKPDN 0x010E
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#define MT6397_TOP_RST_CON 0x0114
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#define MT6397_WRP_CKPDN 0x011A
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#define MT6397_WRP_RST_CON 0x0120
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#define MT6397_TOP_RST_MISC 0x0126
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#define MT6397_TOP_CKCON1 0x0128
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#define MT6397_TOP_CKCON2 0x012A
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#define MT6397_TOP_CKTST1 0x012C
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#define MT6397_TOP_CKTST2 0x012E
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#define MT6397_OC_DEG_EN 0x0130
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#define MT6397_OC_CTL0 0x0132
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#define MT6397_OC_CTL1 0x0134
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#define MT6397_OC_CTL2 0x0136
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#define MT6397_INT_RSV 0x0138
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#define MT6397_TEST_CON0 0x013A
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#define MT6397_TEST_CON1 0x013C
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#define MT6397_STATUS0 0x013E
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#define MT6397_STATUS1 0x0140
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#define MT6397_PGSTATUS 0x0142
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#define MT6397_CHRSTATUS 0x0144
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#define MT6397_OCSTATUS0 0x0146
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#define MT6397_OCSTATUS1 0x0148
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#define MT6397_OCSTATUS2 0x014A
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#define MT6397_HDMI_PAD_IE 0x014C
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#define MT6397_TEST_OUT_L 0x014E
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#define MT6397_TEST_OUT_H 0x0150
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#define MT6397_TDSEL_CON 0x0152
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#define MT6397_RDSEL_CON 0x0154
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#define MT6397_GPIO_SMT_CON0 0x0156
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#define MT6397_GPIO_SMT_CON1 0x0158
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#define MT6397_GPIO_SMT_CON2 0x015A
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#define MT6397_GPIO_SMT_CON3 0x015C
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#define MT6397_DRV_CON0 0x015E
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#define MT6397_DRV_CON1 0x0160
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#define MT6397_DRV_CON2 0x0162
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#define MT6397_DRV_CON3 0x0164
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#define MT6397_DRV_CON4 0x0166
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#define MT6397_DRV_CON5 0x0168
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#define MT6397_DRV_CON6 0x016A
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#define MT6397_DRV_CON7 0x016C
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#define MT6397_DRV_CON8 0x016E
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#define MT6397_DRV_CON9 0x0170
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#define MT6397_DRV_CON10 0x0172
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#define MT6397_DRV_CON11 0x0174
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#define MT6397_DRV_CON12 0x0176
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#define MT6397_INT_CON0 0x0178
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#define MT6397_INT_CON1 0x017E
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#define MT6397_INT_STATUS0 0x0184
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#define MT6397_INT_STATUS1 0x0186
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#define MT6397_FQMTR_CON0 0x0188
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#define MT6397_FQMTR_CON1 0x018A
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#define MT6397_FQMTR_CON2 0x018C
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#define MT6397_EFUSE_DOUT_0_15 0x01C4
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#define MT6397_EFUSE_DOUT_16_31 0x01C6
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#define MT6397_EFUSE_DOUT_32_47 0x01C8
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#define MT6397_EFUSE_DOUT_48_63 0x01CA
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#define MT6397_SPI_CON 0x01CC
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#define MT6397_TOP_CKPDN3 0x01CE
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#define MT6397_TOP_CKCON3 0x01D4
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#define MT6397_EFUSE_DOUT_64_79 0x01D6
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#define MT6397_EFUSE_DOUT_80_95 0x01D8
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#define MT6397_EFUSE_DOUT_96_111 0x01DA
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#define MT6397_EFUSE_DOUT_112_127 0x01DC
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#define MT6397_EFUSE_DOUT_128_143 0x01DE
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#define MT6397_EFUSE_DOUT_144_159 0x01E0
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#define MT6397_EFUSE_DOUT_160_175 0x01E2
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#define MT6397_EFUSE_DOUT_176_191 0x01E4
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#define MT6397_EFUSE_DOUT_192_207 0x01E6
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#define MT6397_EFUSE_DOUT_208_223 0x01E8
|
||||
#define MT6397_EFUSE_DOUT_224_239 0x01EA
|
||||
#define MT6397_EFUSE_DOUT_240_255 0x01EC
|
||||
#define MT6397_EFUSE_DOUT_256_271 0x01EE
|
||||
#define MT6397_EFUSE_DOUT_272_287 0x01F0
|
||||
#define MT6397_EFUSE_DOUT_288_300 0x01F2
|
||||
#define MT6397_EFUSE_DOUT_304_319 0x01F4
|
||||
#define MT6397_BUCK_CON0 0x0200
|
||||
#define MT6397_BUCK_CON1 0x0202
|
||||
#define MT6397_BUCK_CON2 0x0204
|
||||
#define MT6397_BUCK_CON3 0x0206
|
||||
#define MT6397_BUCK_CON4 0x0208
|
||||
#define MT6397_BUCK_CON5 0x020A
|
||||
#define MT6397_BUCK_CON6 0x020C
|
||||
#define MT6397_BUCK_CON7 0x020E
|
||||
#define MT6397_BUCK_CON8 0x0210
|
||||
#define MT6397_BUCK_CON9 0x0212
|
||||
#define MT6397_VCA15_CON0 0x0214
|
||||
#define MT6397_VCA15_CON1 0x0216
|
||||
#define MT6397_VCA15_CON2 0x0218
|
||||
#define MT6397_VCA15_CON3 0x021A
|
||||
#define MT6397_VCA15_CON4 0x021C
|
||||
#define MT6397_VCA15_CON5 0x021E
|
||||
#define MT6397_VCA15_CON6 0x0220
|
||||
#define MT6397_VCA15_CON7 0x0222
|
||||
#define MT6397_VCA15_CON8 0x0224
|
||||
#define MT6397_VCA15_CON9 0x0226
|
||||
#define MT6397_VCA15_CON10 0x0228
|
||||
#define MT6397_VCA15_CON11 0x022A
|
||||
#define MT6397_VCA15_CON12 0x022C
|
||||
#define MT6397_VCA15_CON13 0x022E
|
||||
#define MT6397_VCA15_CON14 0x0230
|
||||
#define MT6397_VCA15_CON15 0x0232
|
||||
#define MT6397_VCA15_CON16 0x0234
|
||||
#define MT6397_VCA15_CON17 0x0236
|
||||
#define MT6397_VCA15_CON18 0x0238
|
||||
#define MT6397_VSRMCA15_CON0 0x023A
|
||||
#define MT6397_VSRMCA15_CON1 0x023C
|
||||
#define MT6397_VSRMCA15_CON2 0x023E
|
||||
#define MT6397_VSRMCA15_CON3 0x0240
|
||||
#define MT6397_VSRMCA15_CON4 0x0242
|
||||
#define MT6397_VSRMCA15_CON5 0x0244
|
||||
#define MT6397_VSRMCA15_CON6 0x0246
|
||||
#define MT6397_VSRMCA15_CON7 0x0248
|
||||
#define MT6397_VSRMCA15_CON8 0x024A
|
||||
#define MT6397_VSRMCA15_CON9 0x024C
|
||||
#define MT6397_VSRMCA15_CON10 0x024E
|
||||
#define MT6397_VSRMCA15_CON11 0x0250
|
||||
#define MT6397_VSRMCA15_CON12 0x0252
|
||||
#define MT6397_VSRMCA15_CON13 0x0254
|
||||
#define MT6397_VSRMCA15_CON14 0x0256
|
||||
#define MT6397_VSRMCA15_CON15 0x0258
|
||||
#define MT6397_VSRMCA15_CON16 0x025A
|
||||
#define MT6397_VSRMCA15_CON17 0x025C
|
||||
#define MT6397_VSRMCA15_CON18 0x025E
|
||||
#define MT6397_VSRMCA15_CON19 0x0260
|
||||
#define MT6397_VSRMCA15_CON20 0x0262
|
||||
#define MT6397_VSRMCA15_CON21 0x0264
|
||||
#define MT6397_VCORE_CON0 0x0266
|
||||
#define MT6397_VCORE_CON1 0x0268
|
||||
#define MT6397_VCORE_CON2 0x026A
|
||||
#define MT6397_VCORE_CON3 0x026C
|
||||
#define MT6397_VCORE_CON4 0x026E
|
||||
#define MT6397_VCORE_CON5 0x0270
|
||||
#define MT6397_VCORE_CON6 0x0272
|
||||
#define MT6397_VCORE_CON7 0x0274
|
||||
#define MT6397_VCORE_CON8 0x0276
|
||||
#define MT6397_VCORE_CON9 0x0278
|
||||
#define MT6397_VCORE_CON10 0x027A
|
||||
#define MT6397_VCORE_CON11 0x027C
|
||||
#define MT6397_VCORE_CON12 0x027E
|
||||
#define MT6397_VCORE_CON13 0x0280
|
||||
#define MT6397_VCORE_CON14 0x0282
|
||||
#define MT6397_VCORE_CON15 0x0284
|
||||
#define MT6397_VCORE_CON16 0x0286
|
||||
#define MT6397_VCORE_CON17 0x0288
|
||||
#define MT6397_VCORE_CON18 0x028A
|
||||
#define MT6397_VGPU_CON0 0x028C
|
||||
#define MT6397_VGPU_CON1 0x028E
|
||||
#define MT6397_VGPU_CON2 0x0290
|
||||
#define MT6397_VGPU_CON3 0x0292
|
||||
#define MT6397_VGPU_CON4 0x0294
|
||||
#define MT6397_VGPU_CON5 0x0296
|
||||
#define MT6397_VGPU_CON6 0x0298
|
||||
#define MT6397_VGPU_CON7 0x029A
|
||||
#define MT6397_VGPU_CON8 0x029C
|
||||
#define MT6397_VGPU_CON9 0x029E
|
||||
#define MT6397_VGPU_CON10 0x02A0
|
||||
#define MT6397_VGPU_CON11 0x02A2
|
||||
#define MT6397_VGPU_CON12 0x02A4
|
||||
#define MT6397_VGPU_CON13 0x02A6
|
||||
#define MT6397_VGPU_CON14 0x02A8
|
||||
#define MT6397_VGPU_CON15 0x02AA
|
||||
#define MT6397_VGPU_CON16 0x02AC
|
||||
#define MT6397_VGPU_CON17 0x02AE
|
||||
#define MT6397_VGPU_CON18 0x02B0
|
||||
#define MT6397_VIO18_CON0 0x0300
|
||||
#define MT6397_VIO18_CON1 0x0302
|
||||
#define MT6397_VIO18_CON2 0x0304
|
||||
#define MT6397_VIO18_CON3 0x0306
|
||||
#define MT6397_VIO18_CON4 0x0308
|
||||
#define MT6397_VIO18_CON5 0x030A
|
||||
#define MT6397_VIO18_CON6 0x030C
|
||||
#define MT6397_VIO18_CON7 0x030E
|
||||
#define MT6397_VIO18_CON8 0x0310
|
||||
#define MT6397_VIO18_CON9 0x0312
|
||||
#define MT6397_VIO18_CON10 0x0314
|
||||
#define MT6397_VIO18_CON11 0x0316
|
||||
#define MT6397_VIO18_CON12 0x0318
|
||||
#define MT6397_VIO18_CON13 0x031A
|
||||
#define MT6397_VIO18_CON14 0x031C
|
||||
#define MT6397_VIO18_CON15 0x031E
|
||||
#define MT6397_VIO18_CON16 0x0320
|
||||
#define MT6397_VIO18_CON17 0x0322
|
||||
#define MT6397_VIO18_CON18 0x0324
|
||||
#define MT6397_VPCA7_CON0 0x0326
|
||||
#define MT6397_VPCA7_CON1 0x0328
|
||||
#define MT6397_VPCA7_CON2 0x032A
|
||||
#define MT6397_VPCA7_CON3 0x032C
|
||||
#define MT6397_VPCA7_CON4 0x032E
|
||||
#define MT6397_VPCA7_CON5 0x0330
|
||||
#define MT6397_VPCA7_CON6 0x0332
|
||||
#define MT6397_VPCA7_CON7 0x0334
|
||||
#define MT6397_VPCA7_CON8 0x0336
|
||||
#define MT6397_VPCA7_CON9 0x0338
|
||||
#define MT6397_VPCA7_CON10 0x033A
|
||||
#define MT6397_VPCA7_CON11 0x033C
|
||||
#define MT6397_VPCA7_CON12 0x033E
|
||||
#define MT6397_VPCA7_CON13 0x0340
|
||||
#define MT6397_VPCA7_CON14 0x0342
|
||||
#define MT6397_VPCA7_CON15 0x0344
|
||||
#define MT6397_VPCA7_CON16 0x0346
|
||||
#define MT6397_VPCA7_CON17 0x0348
|
||||
#define MT6397_VPCA7_CON18 0x034A
|
||||
#define MT6397_VSRMCA7_CON0 0x034C
|
||||
#define MT6397_VSRMCA7_CON1 0x034E
|
||||
#define MT6397_VSRMCA7_CON2 0x0350
|
||||
#define MT6397_VSRMCA7_CON3 0x0352
|
||||
#define MT6397_VSRMCA7_CON4 0x0354
|
||||
#define MT6397_VSRMCA7_CON5 0x0356
|
||||
#define MT6397_VSRMCA7_CON6 0x0358
|
||||
#define MT6397_VSRMCA7_CON7 0x035A
|
||||
#define MT6397_VSRMCA7_CON8 0x035C
|
||||
#define MT6397_VSRMCA7_CON9 0x035E
|
||||
#define MT6397_VSRMCA7_CON10 0x0360
|
||||
#define MT6397_VSRMCA7_CON11 0x0362
|
||||
#define MT6397_VSRMCA7_CON12 0x0364
|
||||
#define MT6397_VSRMCA7_CON13 0x0366
|
||||
#define MT6397_VSRMCA7_CON14 0x0368
|
||||
#define MT6397_VSRMCA7_CON15 0x036A
|
||||
#define MT6397_VSRMCA7_CON16 0x036C
|
||||
#define MT6397_VSRMCA7_CON17 0x036E
|
||||
#define MT6397_VSRMCA7_CON18 0x0370
|
||||
#define MT6397_VSRMCA7_CON19 0x0372
|
||||
#define MT6397_VSRMCA7_CON20 0x0374
|
||||
#define MT6397_VSRMCA7_CON21 0x0376
|
||||
#define MT6397_VDRM_CON0 0x0378
|
||||
#define MT6397_VDRM_CON1 0x037A
|
||||
#define MT6397_VDRM_CON2 0x037C
|
||||
#define MT6397_VDRM_CON3 0x037E
|
||||
#define MT6397_VDRM_CON4 0x0380
|
||||
#define MT6397_VDRM_CON5 0x0382
|
||||
#define MT6397_VDRM_CON6 0x0384
|
||||
#define MT6397_VDRM_CON7 0x0386
|
||||
#define MT6397_VDRM_CON8 0x0388
|
||||
#define MT6397_VDRM_CON9 0x038A
|
||||
#define MT6397_VDRM_CON10 0x038C
|
||||
#define MT6397_VDRM_CON11 0x038E
|
||||
#define MT6397_VDRM_CON12 0x0390
|
||||
#define MT6397_VDRM_CON13 0x0392
|
||||
#define MT6397_VDRM_CON14 0x0394
|
||||
#define MT6397_VDRM_CON15 0x0396
|
||||
#define MT6397_VDRM_CON16 0x0398
|
||||
#define MT6397_VDRM_CON17 0x039A
|
||||
#define MT6397_VDRM_CON18 0x039C
|
||||
#define MT6397_BUCK_K_CON0 0x039E
|
||||
#define MT6397_BUCK_K_CON1 0x03A0
|
||||
#define MT6397_ANALDO_CON0 0x0400
|
||||
#define MT6397_ANALDO_CON1 0x0402
|
||||
#define MT6397_ANALDO_CON2 0x0404
|
||||
#define MT6397_ANALDO_CON3 0x0406
|
||||
#define MT6397_ANALDO_CON4 0x0408
|
||||
#define MT6397_ANALDO_CON5 0x040A
|
||||
#define MT6397_ANALDO_CON6 0x040C
|
||||
#define MT6397_ANALDO_CON7 0x040E
|
||||
#define MT6397_DIGLDO_CON0 0x0410
|
||||
#define MT6397_DIGLDO_CON1 0x0412
|
||||
#define MT6397_DIGLDO_CON2 0x0414
|
||||
#define MT6397_DIGLDO_CON3 0x0416
|
||||
#define MT6397_DIGLDO_CON4 0x0418
|
||||
#define MT6397_DIGLDO_CON5 0x041A
|
||||
#define MT6397_DIGLDO_CON6 0x041C
|
||||
#define MT6397_DIGLDO_CON7 0x041E
|
||||
#define MT6397_DIGLDO_CON8 0x0420
|
||||
#define MT6397_DIGLDO_CON9 0x0422
|
||||
#define MT6397_DIGLDO_CON10 0x0424
|
||||
#define MT6397_DIGLDO_CON11 0x0426
|
||||
#define MT6397_DIGLDO_CON12 0x0428
|
||||
#define MT6397_DIGLDO_CON13 0x042A
|
||||
#define MT6397_DIGLDO_CON14 0x042C
|
||||
#define MT6397_DIGLDO_CON15 0x042E
|
||||
#define MT6397_DIGLDO_CON16 0x0430
|
||||
#define MT6397_DIGLDO_CON17 0x0432
|
||||
#define MT6397_DIGLDO_CON18 0x0434
|
||||
#define MT6397_DIGLDO_CON19 0x0436
|
||||
#define MT6397_DIGLDO_CON20 0x0438
|
||||
#define MT6397_DIGLDO_CON21 0x043A
|
||||
#define MT6397_DIGLDO_CON22 0x043C
|
||||
#define MT6397_DIGLDO_CON23 0x043E
|
||||
#define MT6397_DIGLDO_CON24 0x0440
|
||||
#define MT6397_DIGLDO_CON25 0x0442
|
||||
#define MT6397_DIGLDO_CON26 0x0444
|
||||
#define MT6397_DIGLDO_CON27 0x0446
|
||||
#define MT6397_DIGLDO_CON28 0x0448
|
||||
#define MT6397_DIGLDO_CON29 0x044A
|
||||
#define MT6397_DIGLDO_CON30 0x044C
|
||||
#define MT6397_DIGLDO_CON31 0x044E
|
||||
#define MT6397_DIGLDO_CON32 0x0450
|
||||
#define MT6397_DIGLDO_CON33 0x045A
|
||||
#define MT6397_SPK_CON0 0x0600
|
||||
#define MT6397_SPK_CON1 0x0602
|
||||
#define MT6397_SPK_CON2 0x0604
|
||||
#define MT6397_SPK_CON3 0x0606
|
||||
#define MT6397_SPK_CON4 0x0608
|
||||
#define MT6397_SPK_CON5 0x060A
|
||||
#define MT6397_SPK_CON6 0x060C
|
||||
#define MT6397_SPK_CON7 0x060E
|
||||
#define MT6397_SPK_CON8 0x0610
|
||||
#define MT6397_SPK_CON9 0x0612
|
||||
#define MT6397_SPK_CON10 0x0614
|
||||
#define MT6397_SPK_CON11 0x0616
|
||||
#define MT6397_AUDDAC_CON0 0x0700
|
||||
#define MT6397_AUDBUF_CFG0 0x0702
|
||||
#define MT6397_AUDBUF_CFG1 0x0704
|
||||
#define MT6397_AUDBUF_CFG2 0x0706
|
||||
#define MT6397_AUDBUF_CFG3 0x0708
|
||||
#define MT6397_AUDBUF_CFG4 0x070A
|
||||
#define MT6397_IBIASDIST_CFG0 0x070C
|
||||
#define MT6397_AUDACCDEPOP_CFG0 0x070E
|
||||
#define MT6397_AUD_IV_CFG0 0x0710
|
||||
#define MT6397_AUDCLKGEN_CFG0 0x0712
|
||||
#define MT6397_AUDLDO_CFG0 0x0714
|
||||
#define MT6397_AUDLDO_CFG1 0x0716
|
||||
#define MT6397_AUDNVREGGLB_CFG0 0x0718
|
||||
#define MT6397_AUD_NCP0 0x071A
|
||||
#define MT6397_AUDPREAMP_CON0 0x071C
|
||||
#define MT6397_AUDADC_CON0 0x071E
|
||||
#define MT6397_AUDADC_CON1 0x0720
|
||||
#define MT6397_AUDADC_CON2 0x0722
|
||||
#define MT6397_AUDADC_CON3 0x0724
|
||||
#define MT6397_AUDADC_CON4 0x0726
|
||||
#define MT6397_AUDADC_CON5 0x0728
|
||||
#define MT6397_AUDADC_CON6 0x072A
|
||||
#define MT6397_AUDDIGMI_CON0 0x072C
|
||||
#define MT6397_AUDLSBUF_CON0 0x072E
|
||||
#define MT6397_AUDLSBUF_CON1 0x0730
|
||||
#define MT6397_AUDENCSPARE_CON0 0x0732
|
||||
#define MT6397_AUDENCCLKSQ_CON0 0x0734
|
||||
#define MT6397_AUDPREAMPGAIN_CON0 0x0736
|
||||
#define MT6397_ZCD_CON0 0x0738
|
||||
#define MT6397_ZCD_CON1 0x073A
|
||||
#define MT6397_ZCD_CON2 0x073C
|
||||
#define MT6397_ZCD_CON3 0x073E
|
||||
#define MT6397_ZCD_CON4 0x0740
|
||||
#define MT6397_ZCD_CON5 0x0742
|
||||
#define MT6397_NCP_CLKDIV_CON0 0x0744
|
||||
#define MT6397_NCP_CLKDIV_CON1 0x0746
|
||||
|
||||
#endif /* __MFD_MT6397_REGISTERS_H__ */
|
||||
Loading…
Reference in a new issue