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ARC: [axs10x] cap ethernet phy to 100 Mbit/sec

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Current ARC SDP boards cannot reliably handle 1Gbit
Ethernet connections due to limitations in hardware.

To make sure networking is stable on the board we're
limiting phy to 100 Mbit.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Alexey Brodkin 2015-12-07 14:21:37 +03:00 committed by Vineet Gupta
parent 31ade3b83e
commit 6d1a2adef7
1 changed files with 1 additions and 0 deletions
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arch/arc/boot/dts/axs10x_mb.dtsi
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@ -46,6 +46,7 @@ ethernet@0x18000 {
snps,pbl = < 32 >; snps,pbl = < 32 >;
clocks = <&apbclk>; clocks = <&apbclk>;
clock-names = "stmmaceth"; clock-names = "stmmaceth";
max-speed = <100>;
}; };
ehci@0x40000 { ehci@0x40000 {