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ARM: tegra: core SoC support development
This branch includes major development on the core Tegra SoC support code in the mach-tegra directory: * SMP support for Tegra114. * Exposes SoC chip ID and revision through standard sysfs files. * System-level suspend/resume for Tegra20/30. At present, this only supports "LP2" mode (CPU power-down), but provides the basis to implement "LP0"/"LP1" (various levels of core/chip power-down) in the hopefully near future. * A minor cleanup of a duplicate include, which was introduced in this branch. This branch is based on the previous cleanup pull request. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJRXvvtAAoJEMzrak5tbycxwdAP/ioto6+ekXniT3/Iqx9CmqG4 kDwS6LKn8Y91ePH6R8i23U98PjLwo/HgRWSTLjfwLMAi3AOEgsJ+bUnCmPAszxkY Ayyv+SLbgYaR817ezACXKH0tJHF1yo07bwk76jXQwo9/d71wg8sLweQwuEA1p/u8 ZlMniF731p7oZCNcoK680eFsurTO850GTfCrBowmOiGcPgpbllTEifwRthzQNhD7 b0Yw55rTqz9gbhgYCN33Va6CzwD9CMaxKN28J6qPJ+j7JCXO5Qp2QCuQ5PxLTbGq g1n65h2p5eXQwJwnf70jGuvF9xjdPO0zNTbQVP/hkrRMpB9VA0Z6zw0s12c1H70l Hs/7Hn7IBzCf5jdn802knc0K0b3Q7MhUjfTU6Gmj2KWJ+SfjMQtfqRdTWKsmPXXU 3MVxlJnqHNCjttWXXkxN0lKSgdi5HN431RwD6P9i0NPIq9RKZutw4jFeNLclVuGa xZMBtdDZ/U2KwL0aITkleacMHcb5/pK1z626//rB2CWRSRtVLGgye14FyEBi1U+I EdA16bu9U6MiwlqT0I849pXFb3l0di0+FTVadE+D3aJGjk/IWond0Fk1VayaSCX0 X8SNUByRPtwhJRQH+oX+HDZXWW6gc2cixpYSoDmgdSXSJLBuLlAD+KPAXi2hvTUf REyjYXwVXVyMY/XTz5fP =1KXE -----END PGP SIGNATURE----- Merge tag 'tegra-for-3.10-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc From Stephen Warren <swarren@wwwdotorg.org>: ARM: tegra: core SoC support development This branch includes major development on the core Tegra SoC support code in the mach-tegra directory: * SMP support for Tegra114. * Exposes SoC chip ID and revision through standard sysfs files. * System-level suspend/resume for Tegra20/30. At present, this only supports "LP2" mode (CPU power-down), but provides the basis to implement "LP0"/"LP1" (various levels of core/chip power-down) in the hopefully near future. * A minor cleanup of a duplicate include, which was introduced in this branch. This branch is based on the previous cleanup pull request. * tag 'tegra-for-3.10-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: ARM: tegra: pm: remove duplicated include from pm.c ARM: tegra: cpuidle: remove redundant parameters for powered-down mode ARM: tegra: pm: add platform suspend support ARM: dt: tegra: add bindings of power management configurations for PMC ARM: tegra: irq: add wake up handling gpio: tegra: add gpio wakeup source handling ARM: tegra: moving the CPU power timer function to PMC driver ARM: tegra: add clock source of PMC to device trees ARM: tegra: add speedo-based process id for Tegra114 ARM: tegra: expose chip ID and revision ARM: tegra: bring up secondary CPU for Tegra114 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
6cd2f8e7da
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@ -1,19 +1,84 @@
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NVIDIA Tegra Power Management Controller (PMC)
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Properties:
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The PMC block interacts with an external Power Management Unit. The PMC
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mostly controls the entry and exit of the system from different sleep
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modes. It provides power-gating controllers for SoC and CPU power-islands.
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Required properties:
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- name : Should be pmc
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- compatible : Should contain "nvidia,tegra<chip>-pmc".
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- reg : Offset and length of the register set for the device
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- clocks : Must contain an entry for each entry in clock-names.
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- clock-names : Must include the following entries:
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"pclk" (The Tegra clock of that name),
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"clk32k_in" (The 32KHz clock input to Tegra).
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Optional properties:
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- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
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The PMU is an external Power Management Unit, whose interrupt output
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signal is fed into the PMC. This signal is optionally inverted, and then
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fed into the ARM GIC. The PMC is not involved in the detection or
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handling of this interrupt signal, merely its inversion.
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- nvidia,suspend-mode : The suspend mode that the platform should use.
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Valid values are 0, 1 and 2:
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0 (LP0): CPU + Core voltage off and DRAM in self-refresh
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1 (LP1): CPU voltage off and DRAM in self-refresh
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2 (LP2): CPU voltage off
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- nvidia,core-power-req-active-high : Boolean, core power request active-high
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- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high
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- nvidia,combined-power-req : Boolean, combined power request for CPU & Core
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- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
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is enabled.
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Required properties when nvidia,suspend-mode is specified:
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- nvidia,cpu-pwr-good-time : CPU power good time in uS.
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- nvidia,cpu-pwr-off-time : CPU power off time in uS.
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- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time>
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Core power good time in uS.
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- nvidia,core-pwr-off-time : Core power off time in uS.
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Required properties when nvidia,suspend-mode=<0>:
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- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector
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The LP0 vector contains the warm boot code that is executed by AVP when
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resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7
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processor and always being the first boot processor when chip is power on
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or resume from deep sleep mode. When the system is resumed from the deep
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sleep mode, the warm boot code will restore some PLLs, clocks and then
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bring up CPU0 for resuming the system.
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Example:
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/ SoC dts including file
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pmc@7000f400 {
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compatible = "nvidia,tegra20-pmc";
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reg = <0x7000e400 0x400>;
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clocks = <&tegra_car 110>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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nvidia,invert-interrupt;
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nvidia,suspend-mode = <1>;
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nvidia,cpu-pwr-good-time = <2000>;
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nvidia,cpu-pwr-off-time = <100>;
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nvidia,core-pwr-good-time = <3845 3845>;
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nvidia,core-pwr-off-time = <458>;
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nvidia,core-power-req-active-high;
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nvidia,sys-clock-req-active-high;
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nvidia,lp0-vec = <0xbdffd000 0x2000>;
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};
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/ Tegra board dts file
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{
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...
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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clk32k_in: clock {
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compatible = "fixed-clock";
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reg=<0>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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...
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};
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@ -673,6 +673,7 @@ config ARCH_TEGRA
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select HAVE_CLK
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select HAVE_SMP
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select MIGHT_HAVE_CACHE_L2X0
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select SOC_BUS
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select SPARSE_IRQ
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select USE_OF
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help
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@ -18,4 +18,17 @@ serial@70006300 {
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pmc {
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nvidia,invert-interrupt;
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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clk32k_in: clock {
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compatible = "fixed-clock";
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reg=<0>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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};
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|
|
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@ -18,4 +18,17 @@ serial@70006300 {
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pmc {
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nvidia,invert-interrupt;
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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clk32k_in: clock {
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compatible = "fixed-clock";
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reg=<0>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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};
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|
|
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@ -101,6 +101,8 @@ rtc {
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pmc {
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compatible = "nvidia,tegra114-pmc";
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reg = <0x7000e400 0x400>;
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clocks = <&tegra_car 261>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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};
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iommu {
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|
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@ -447,6 +447,19 @@ sdhci@c8000600 {
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cd-gpios = <&gpio 23 1>; /* gpio PC7 */
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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clk32k_in: clock {
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compatible = "fixed-clock";
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reg=<0>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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sound {
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compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
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"nvidia,tegra-audio-wm9712";
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|
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@ -451,6 +451,19 @@ sdhci@c8000600 {
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bus-width = <8>;
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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clk32k_in: clock {
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compatible = "fixed-clock";
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reg=<0>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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kbc {
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status = "okay";
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nvidia,debounce-delay-ms = <2>;
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@ -447,6 +447,19 @@ sdhci@c8000600 {
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bus-width = <8>;
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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clk32k_in: clock {
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compatible = "fixed-clock";
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reg=<0>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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|
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@ -595,6 +595,19 @@ sdhci@c8000600 {
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bus-width = <8>;
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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clk32k_in: clock {
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compatible = "fixed-clock";
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reg=<0>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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|
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@ -471,6 +471,19 @@ sdhci@c8000600 {
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status = "okay";
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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clk32k_in: clock {
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compatible = "fixed-clock";
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reg=<0>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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regulators {
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compatible = "simple-bus";
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|
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@ -330,6 +330,19 @@ sdhci@c8000600 {
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bus-width = <4>;
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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clk32k_in: clock {
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compatible = "fixed-clock";
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reg=<0>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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poweroff {
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compatible = "gpio-poweroff";
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gpios = <&gpio 191 1>; /* gpio PX7, active low */
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|
|
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@ -531,6 +531,19 @@ sdhci@c8000600 {
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bus-width = <8>;
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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clk32k_in: clock {
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compatible = "fixed-clock";
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reg=<0>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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|
|
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|
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@ -520,6 +520,19 @@ sdhci@c8000600 {
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bus-width = <8>;
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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clk32k_in: clock {
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compatible = "fixed-clock";
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reg=<0>;
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#clock-cells = <0>;
|
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clock-frequency = <32768>;
|
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};
|
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};
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kbc {
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status = "okay";
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nvidia,debounce-delay-ms = <20>;
|
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|
|
|
|||
|
|
@ -418,6 +418,8 @@ kbc {
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pmc {
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compatible = "nvidia,tegra20-pmc";
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reg = <0x7000e400 0x400>;
|
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clocks = <&tegra_car 110>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
|
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};
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||||
|
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memory-controller@7000f000 {
|
||||
|
|
|
|||
|
|
@ -268,6 +268,19 @@ sdhci@78000600 {
|
|||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -322,6 +322,19 @@ sdhci@78000600 {
|
|||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -427,6 +427,8 @@ kbc {
|
|||
pmc {
|
||||
compatible = "nvidia,tegra30-pmc";
|
||||
reg = <0x7000e400 0x400>;
|
||||
clocks = <&tegra_car 218>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
};
|
||||
|
||||
memory-controller {
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
|||
obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o
|
||||
obj-$(CONFIG_TEGRA_PCI) += pcie.o
|
||||
|
||||
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114_speedo.o
|
||||
ifeq ($(CONFIG_CPU_IDLE),y)
|
||||
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@
|
|||
#include "common.h"
|
||||
#include "fuse.h"
|
||||
#include "iomap.h"
|
||||
#include "irq.h"
|
||||
#include "pmc.h"
|
||||
#include "apbio.h"
|
||||
#include "sleep.h"
|
||||
|
|
@ -61,8 +62,10 @@ u32 tegra_uart_config[4] = {
|
|||
void __init tegra_dt_init_irq(void)
|
||||
{
|
||||
tegra_clocks_init();
|
||||
tegra_pmc_init();
|
||||
tegra_init_irq();
|
||||
irqchip_init();
|
||||
tegra_legacy_irq_syscore_init();
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -100,12 +103,12 @@ void __init tegra_init_early(void)
|
|||
tegra_apb_io_init();
|
||||
tegra_init_fuse();
|
||||
tegra_init_cache();
|
||||
tegra_pmc_init();
|
||||
tegra_powergate_init();
|
||||
tegra_hotplug_init();
|
||||
}
|
||||
|
||||
void __init tegra_init_late(void)
|
||||
{
|
||||
tegra_init_suspend();
|
||||
tegra_powergate_debugfs_init();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -130,10 +130,6 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
|
|||
struct cpuidle_driver *drv,
|
||||
int index)
|
||||
{
|
||||
struct cpuidle_state *state = &drv->states[index];
|
||||
u32 cpu_on_time = state->exit_latency;
|
||||
u32 cpu_off_time = state->target_residency - state->exit_latency;
|
||||
|
||||
while (tegra20_cpu_is_resettable_soon())
|
||||
cpu_relax();
|
||||
|
||||
|
|
@ -142,7 +138,7 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
|
|||
|
||||
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
|
||||
|
||||
tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
|
||||
tegra_idle_lp2_last();
|
||||
|
||||
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
|
||||
|
||||
|
|
|
|||
|
|
@ -72,10 +72,6 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
|
|||
struct cpuidle_driver *drv,
|
||||
int index)
|
||||
{
|
||||
struct cpuidle_state *state = &drv->states[index];
|
||||
u32 cpu_on_time = state->exit_latency;
|
||||
u32 cpu_off_time = state->target_residency - state->exit_latency;
|
||||
|
||||
/* All CPUs entering LP2 is not working.
|
||||
* Don't let CPU0 enter LP2 when any secondary CPU is online.
|
||||
*/
|
||||
|
|
@ -86,7 +82,7 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
|
|||
|
||||
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
|
||||
|
||||
tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
|
||||
tegra_idle_lp2_last();
|
||||
|
||||
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
|
||||
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
* arch/arm/mach-tegra/fuse.c
|
||||
*
|
||||
* Copyright (C) 2010 Google, Inc.
|
||||
* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Author:
|
||||
* Colin Cross <ccross@android.com>
|
||||
|
|
@ -137,6 +138,9 @@ void tegra_init_fuse(void)
|
|||
tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT;
|
||||
tegra_init_speedo_data = &tegra30_init_speedo_data;
|
||||
break;
|
||||
case TEGRA114:
|
||||
tegra_init_speedo_data = &tegra114_init_speedo_data;
|
||||
break;
|
||||
default:
|
||||
pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id);
|
||||
tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
/*
|
||||
* Copyright (C) 2010 Google, Inc.
|
||||
* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Author:
|
||||
* Colin Cross <ccross@android.com>
|
||||
|
|
@ -66,4 +67,10 @@ void tegra30_init_speedo_data(void);
|
|||
static inline void tegra30_init_speedo_data(void) {}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_114_SOC
|
||||
void tegra114_init_speedo_data(void);
|
||||
#else
|
||||
static inline void tegra114_init_speedo_data(void) {}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* Author:
|
||||
* Colin Cross <ccross@android.com>
|
||||
*
|
||||
* Copyright (C) 2010, NVIDIA Corporation
|
||||
* Copyright (C) 2010,2013, NVIDIA Corporation
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
|
|
@ -23,6 +23,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include "board.h"
|
||||
#include "iomap.h"
|
||||
|
|
@ -43,6 +44,7 @@
|
|||
#define ICTLR_COP_IEP_CLASS 0x3c
|
||||
|
||||
#define FIRST_LEGACY_IRQ 32
|
||||
#define TEGRA_MAX_NUM_ICTLRS 5
|
||||
|
||||
#define SGI_MASK 0xFFFF
|
||||
|
||||
|
|
@ -56,6 +58,15 @@ static void __iomem *ictlr_reg_base[] = {
|
|||
IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
|
||||
static u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
|
||||
static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
|
||||
static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
|
||||
|
||||
static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
|
||||
#endif
|
||||
|
||||
bool tegra_pending_sgi(void)
|
||||
{
|
||||
u32 pending_set;
|
||||
|
|
@ -125,6 +136,87 @@ static int tegra_retrigger(struct irq_data *d)
|
|||
return 1;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int tegra_set_wake(struct irq_data *d, unsigned int enable)
|
||||
{
|
||||
u32 irq = d->irq;
|
||||
u32 index, mask;
|
||||
|
||||
if (irq < FIRST_LEGACY_IRQ ||
|
||||
irq >= FIRST_LEGACY_IRQ + num_ictlrs * 32)
|
||||
return -EINVAL;
|
||||
|
||||
index = ((irq - FIRST_LEGACY_IRQ) / 32);
|
||||
mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
|
||||
if (enable)
|
||||
ictlr_wake_mask[index] |= mask;
|
||||
else
|
||||
ictlr_wake_mask[index] &= ~mask;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_legacy_irq_suspend(void)
|
||||
{
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
local_irq_save(flags);
|
||||
for (i = 0; i < num_ictlrs; i++) {
|
||||
void __iomem *ictlr = ictlr_reg_base[i];
|
||||
/* Save interrupt state */
|
||||
cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
|
||||
cpu_iep[i] = readl_relaxed(ictlr + ICTLR_CPU_IEP_CLASS);
|
||||
cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);
|
||||
cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
|
||||
|
||||
/* Disable COP interrupts */
|
||||
writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
|
||||
|
||||
/* Disable CPU interrupts */
|
||||
writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
|
||||
|
||||
/* Enable the wakeup sources of ictlr */
|
||||
writel_relaxed(ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET);
|
||||
}
|
||||
local_irq_restore(flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void tegra_legacy_irq_resume(void)
|
||||
{
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
local_irq_save(flags);
|
||||
for (i = 0; i < num_ictlrs; i++) {
|
||||
void __iomem *ictlr = ictlr_reg_base[i];
|
||||
writel_relaxed(cpu_iep[i], ictlr + ICTLR_CPU_IEP_CLASS);
|
||||
writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
|
||||
writel_relaxed(cpu_ier[i], ictlr + ICTLR_CPU_IER_SET);
|
||||
writel_relaxed(cop_iep[i], ictlr + ICTLR_COP_IEP_CLASS);
|
||||
writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
|
||||
writel_relaxed(cop_ier[i], ictlr + ICTLR_COP_IER_SET);
|
||||
}
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static struct syscore_ops tegra_legacy_irq_syscore_ops = {
|
||||
.suspend = tegra_legacy_irq_suspend,
|
||||
.resume = tegra_legacy_irq_resume,
|
||||
};
|
||||
|
||||
int tegra_legacy_irq_syscore_init(void)
|
||||
{
|
||||
register_syscore_ops(&tegra_legacy_irq_syscore_ops);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
#define tegra_set_wake NULL
|
||||
#endif
|
||||
|
||||
void __init tegra_init_irq(void)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -150,6 +242,8 @@ void __init tegra_init_irq(void)
|
|||
gic_arch_extn.irq_mask = tegra_mask;
|
||||
gic_arch_extn.irq_unmask = tegra_unmask;
|
||||
gic_arch_extn.irq_retrigger = tegra_retrigger;
|
||||
gic_arch_extn.irq_set_wake = tegra_set_wake;
|
||||
gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
|
||||
|
||||
/*
|
||||
* Check if there is a devicetree present, since the GIC will be
|
||||
|
|
|
|||
|
|
@ -19,4 +19,10 @@
|
|||
|
||||
bool tegra_pending_sgi(void);
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
int tegra_legacy_irq_syscore_init(void);
|
||||
#else
|
||||
static inline int tegra_legacy_irq_syscore_init(void) { return 0; }
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -146,6 +146,12 @@ static int tegra30_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
cpu = cpu_logical_map(cpu);
|
||||
return tegra_pmc_cpu_power_on(cpu);
|
||||
}
|
||||
|
||||
static int __cpuinit tegra_boot_secondary(unsigned int cpu,
|
||||
struct task_struct *idle)
|
||||
{
|
||||
|
|
@ -153,6 +159,8 @@ static int __cpuinit tegra_boot_secondary(unsigned int cpu,
|
|||
return tegra20_boot_secondary(cpu, idle);
|
||||
if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30)
|
||||
return tegra30_boot_secondary(cpu, idle);
|
||||
if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114)
|
||||
return tegra114_boot_secondary(cpu, idle);
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
#include <linux/cpumask.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/cpu_pm.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/suspend.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk/tegra.h>
|
||||
|
||||
|
|
@ -37,52 +37,13 @@
|
|||
#include "reset.h"
|
||||
#include "flowctrl.h"
|
||||
#include "fuse.h"
|
||||
#include "pmc.h"
|
||||
#include "sleep.h"
|
||||
|
||||
#define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */
|
||||
|
||||
#define PMC_CTRL 0x0
|
||||
#define PMC_CPUPWRGOOD_TIMER 0xc8
|
||||
#define PMC_CPUPWROFF_TIMER 0xcc
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static DEFINE_SPINLOCK(tegra_lp2_lock);
|
||||
static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
|
||||
static struct clk *tegra_pclk;
|
||||
void (*tegra_tear_down_cpu)(void);
|
||||
|
||||
static void set_power_timers(unsigned long us_on, unsigned long us_off)
|
||||
{
|
||||
unsigned long long ticks;
|
||||
unsigned long long pclk;
|
||||
unsigned long rate;
|
||||
static unsigned long tegra_last_pclk;
|
||||
|
||||
if (tegra_pclk == NULL) {
|
||||
tegra_pclk = clk_get_sys(NULL, "pclk");
|
||||
WARN_ON(IS_ERR(tegra_pclk));
|
||||
}
|
||||
|
||||
rate = clk_get_rate(tegra_pclk);
|
||||
|
||||
if (WARN_ON_ONCE(rate <= 0))
|
||||
pclk = 100000000;
|
||||
else
|
||||
pclk = rate;
|
||||
|
||||
if ((rate != tegra_last_pclk)) {
|
||||
ticks = (us_on * pclk) + 999999ull;
|
||||
do_div(ticks, 1000000);
|
||||
writel((unsigned long)ticks, pmc + PMC_CPUPWRGOOD_TIMER);
|
||||
|
||||
ticks = (us_off * pclk) + 999999ull;
|
||||
do_div(ticks, 1000000);
|
||||
writel((unsigned long)ticks, pmc + PMC_CPUPWROFF_TIMER);
|
||||
wmb();
|
||||
}
|
||||
tegra_last_pclk = pclk;
|
||||
}
|
||||
|
||||
/*
|
||||
* restore_cpu_complex
|
||||
*
|
||||
|
|
@ -173,16 +134,9 @@ static int tegra_sleep_cpu(unsigned long v2p)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time)
|
||||
void tegra_idle_lp2_last(void)
|
||||
{
|
||||
u32 mode;
|
||||
|
||||
/* Only the last cpu down does the final suspend steps */
|
||||
mode = readl(pmc + PMC_CTRL);
|
||||
mode |= TEGRA_POWER_CPU_PWRREQ_OE;
|
||||
writel(mode, pmc + PMC_CTRL);
|
||||
|
||||
set_power_timers(cpu_on_time, cpu_off_time);
|
||||
tegra_pmc_pm_set(TEGRA_SUSPEND_LP2);
|
||||
|
||||
cpu_cluster_pm_enter();
|
||||
suspend_cpu_complex();
|
||||
|
|
@ -192,4 +146,81 @@ void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time)
|
|||
restore_cpu_complex();
|
||||
cpu_cluster_pm_exit();
|
||||
}
|
||||
|
||||
enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
|
||||
enum tegra_suspend_mode mode)
|
||||
{
|
||||
/* Tegra114 didn't support any suspending mode yet. */
|
||||
if (tegra_chip_id == TEGRA114)
|
||||
return TEGRA_SUSPEND_NONE;
|
||||
|
||||
/*
|
||||
* The Tegra devices only support suspending to LP2 currently.
|
||||
*/
|
||||
if (mode > TEGRA_SUSPEND_LP2)
|
||||
return TEGRA_SUSPEND_LP2;
|
||||
|
||||
return mode;
|
||||
}
|
||||
|
||||
static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
|
||||
[TEGRA_SUSPEND_NONE] = "none",
|
||||
[TEGRA_SUSPEND_LP2] = "LP2",
|
||||
[TEGRA_SUSPEND_LP1] = "LP1",
|
||||
[TEGRA_SUSPEND_LP0] = "LP0",
|
||||
};
|
||||
|
||||
static int __cpuinit tegra_suspend_enter(suspend_state_t state)
|
||||
{
|
||||
enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
|
||||
|
||||
if (WARN_ON(mode < TEGRA_SUSPEND_NONE ||
|
||||
mode >= TEGRA_MAX_SUSPEND_MODE))
|
||||
return -EINVAL;
|
||||
|
||||
pr_info("Entering suspend state %s\n", lp_state[mode]);
|
||||
|
||||
tegra_pmc_pm_set(mode);
|
||||
|
||||
local_fiq_disable();
|
||||
|
||||
suspend_cpu_complex();
|
||||
switch (mode) {
|
||||
case TEGRA_SUSPEND_LP2:
|
||||
tegra_set_cpu_in_lp2(0);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
|
||||
|
||||
switch (mode) {
|
||||
case TEGRA_SUSPEND_LP2:
|
||||
tegra_clear_cpu_in_lp2(0);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
restore_cpu_complex();
|
||||
|
||||
local_fiq_enable();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct platform_suspend_ops tegra_suspend_ops = {
|
||||
.valid = suspend_valid_only_mem,
|
||||
.enter = tegra_suspend_enter,
|
||||
};
|
||||
|
||||
void __init tegra_init_suspend(void)
|
||||
{
|
||||
if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NONE)
|
||||
return;
|
||||
|
||||
tegra_pmc_suspend_init();
|
||||
|
||||
suspend_set_ops(&tegra_suspend_ops);
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -21,6 +21,8 @@
|
|||
#ifndef _MACH_TEGRA_PM_H_
|
||||
#define _MACH_TEGRA_PM_H_
|
||||
|
||||
#include "pmc.h"
|
||||
|
||||
extern unsigned long l2x0_saved_regs_addr;
|
||||
|
||||
void save_cpu_arch_register(void);
|
||||
|
|
@ -29,7 +31,20 @@ void restore_cpu_arch_register(void);
|
|||
void tegra_clear_cpu_in_lp2(int phy_cpu_id);
|
||||
bool tegra_set_cpu_in_lp2(int phy_cpu_id);
|
||||
|
||||
void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time);
|
||||
void tegra_idle_lp2_last(void);
|
||||
extern void (*tegra_tear_down_cpu)(void);
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
|
||||
enum tegra_suspend_mode mode);
|
||||
void tegra_init_suspend(void);
|
||||
#else
|
||||
enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
|
||||
enum tegra_suspend_mode mode)
|
||||
{
|
||||
return TEGRA_SUSPEND_NONE;
|
||||
}
|
||||
static inline void tegra_init_suspend(void) {}
|
||||
#endif
|
||||
|
||||
#endif /* _MACH_TEGRA_PM_H_ */
|
||||
|
|
|
|||
|
|
@ -16,10 +16,20 @@
|
|||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include "fuse.h"
|
||||
#include "pm.h"
|
||||
#include "pmc.h"
|
||||
#include "sleep.h"
|
||||
|
||||
#define TEGRA_POWER_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */
|
||||
#define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */
|
||||
#define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */
|
||||
|
||||
#define PMC_CTRL 0x0
|
||||
#define PMC_CTRL_INTR_LOW (1 << 17)
|
||||
#define PMC_PWRGATE_TOGGLE 0x30
|
||||
|
|
@ -27,6 +37,9 @@
|
|||
#define PMC_REMOVE_CLAMPING 0x34
|
||||
#define PMC_PWRGATE_STATUS 0x38
|
||||
|
||||
#define PMC_CPUPWRGOOD_TIMER 0xc8
|
||||
#define PMC_CPUPWROFF_TIMER 0xcc
|
||||
|
||||
#define TEGRA_POWERGATE_PCIE 3
|
||||
#define TEGRA_POWERGATE_VDEC 4
|
||||
#define TEGRA_POWERGATE_CPU1 9
|
||||
|
|
@ -43,6 +56,23 @@ static DEFINE_SPINLOCK(tegra_powergate_lock);
|
|||
|
||||
static void __iomem *tegra_pmc_base;
|
||||
static bool tegra_pmc_invert_interrupt;
|
||||
static struct clk *tegra_pclk;
|
||||
|
||||
struct pmc_pm_data {
|
||||
u32 cpu_good_time; /* CPU power good time in uS */
|
||||
u32 cpu_off_time; /* CPU power off time in uS */
|
||||
u32 core_osc_time; /* Core power good osc time in uS */
|
||||
u32 core_pmu_time; /* Core power good pmu time in uS */
|
||||
u32 core_off_time; /* Core power off time in uS */
|
||||
bool corereq_high; /* Core power request active-high */
|
||||
bool sysclkreq_high; /* System clock request active-high */
|
||||
bool combined_req; /* Combined pwr req for CPU & Core */
|
||||
bool cpu_pwr_good_en; /* CPU power good signal is enabled */
|
||||
u32 lp0_vec_phy_addr; /* The phy addr of LP0 warm boot code */
|
||||
u32 lp0_vec_size; /* The size of LP0 warm boot code */
|
||||
enum tegra_suspend_mode suspend_mode;
|
||||
};
|
||||
static struct pmc_pm_data pmc_pm_data;
|
||||
|
||||
static inline u32 tegra_pmc_readl(u32 reg)
|
||||
{
|
||||
|
|
@ -133,6 +163,70 @@ int tegra_pmc_cpu_remove_clamping(int cpuid)
|
|||
return tegra_pmc_powergate_remove_clamping(id);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate)
|
||||
{
|
||||
unsigned long long ticks;
|
||||
unsigned long long pclk;
|
||||
static unsigned long tegra_last_pclk;
|
||||
|
||||
if (WARN_ON_ONCE(rate <= 0))
|
||||
pclk = 100000000;
|
||||
else
|
||||
pclk = rate;
|
||||
|
||||
if ((rate != tegra_last_pclk)) {
|
||||
ticks = (us_on * pclk) + 999999ull;
|
||||
do_div(ticks, 1000000);
|
||||
tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWRGOOD_TIMER);
|
||||
|
||||
ticks = (us_off * pclk) + 999999ull;
|
||||
do_div(ticks, 1000000);
|
||||
tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWROFF_TIMER);
|
||||
wmb();
|
||||
}
|
||||
tegra_last_pclk = pclk;
|
||||
}
|
||||
|
||||
enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
|
||||
{
|
||||
return pmc_pm_data.suspend_mode;
|
||||
}
|
||||
|
||||
void tegra_pmc_pm_set(enum tegra_suspend_mode mode)
|
||||
{
|
||||
u32 reg;
|
||||
unsigned long rate = 0;
|
||||
|
||||
reg = tegra_pmc_readl(PMC_CTRL);
|
||||
reg |= TEGRA_POWER_CPU_PWRREQ_OE;
|
||||
reg &= ~TEGRA_POWER_EFFECT_LP0;
|
||||
|
||||
switch (mode) {
|
||||
case TEGRA_SUSPEND_LP2:
|
||||
rate = clk_get_rate(tegra_pclk);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
set_power_timers(pmc_pm_data.cpu_good_time, pmc_pm_data.cpu_off_time,
|
||||
rate);
|
||||
|
||||
tegra_pmc_writel(reg, PMC_CTRL);
|
||||
}
|
||||
|
||||
void tegra_pmc_suspend_init(void)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
/* Always enable CPU power request */
|
||||
reg = tegra_pmc_readl(PMC_CTRL);
|
||||
reg |= TEGRA_POWER_CPU_PWRREQ_OE;
|
||||
tegra_pmc_writel(reg, PMC_CTRL);
|
||||
}
|
||||
#endif
|
||||
|
||||
static const struct of_device_id matches[] __initconst = {
|
||||
{ .compatible = "nvidia,tegra114-pmc" },
|
||||
{ .compatible = "nvidia,tegra30-pmc" },
|
||||
|
|
@ -143,6 +237,10 @@ static const struct of_device_id matches[] __initconst = {
|
|||
static void tegra_pmc_parse_dt(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
u32 prop;
|
||||
enum tegra_suspend_mode suspend_mode;
|
||||
u32 core_good_time[2] = {0, 0};
|
||||
u32 lp0_vec[2] = {0, 0};
|
||||
|
||||
np = of_find_matching_node(NULL, matches);
|
||||
BUG_ON(!np);
|
||||
|
|
@ -151,6 +249,70 @@ static void tegra_pmc_parse_dt(void)
|
|||
|
||||
tegra_pmc_invert_interrupt = of_property_read_bool(np,
|
||||
"nvidia,invert-interrupt");
|
||||
tegra_pclk = of_clk_get_by_name(np, "pclk");
|
||||
WARN_ON(IS_ERR(tegra_pclk));
|
||||
|
||||
/* Grabbing the power management configurations */
|
||||
if (of_property_read_u32(np, "nvidia,suspend-mode", &prop)) {
|
||||
suspend_mode = TEGRA_SUSPEND_NONE;
|
||||
} else {
|
||||
switch (prop) {
|
||||
case 0:
|
||||
suspend_mode = TEGRA_SUSPEND_LP0;
|
||||
break;
|
||||
case 1:
|
||||
suspend_mode = TEGRA_SUSPEND_LP1;
|
||||
break;
|
||||
case 2:
|
||||
suspend_mode = TEGRA_SUSPEND_LP2;
|
||||
break;
|
||||
default:
|
||||
suspend_mode = TEGRA_SUSPEND_NONE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
suspend_mode = tegra_pm_validate_suspend_mode(suspend_mode);
|
||||
|
||||
if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &prop))
|
||||
suspend_mode = TEGRA_SUSPEND_NONE;
|
||||
pmc_pm_data.cpu_good_time = prop;
|
||||
|
||||
if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &prop))
|
||||
suspend_mode = TEGRA_SUSPEND_NONE;
|
||||
pmc_pm_data.cpu_off_time = prop;
|
||||
|
||||
if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
|
||||
core_good_time, ARRAY_SIZE(core_good_time)))
|
||||
suspend_mode = TEGRA_SUSPEND_NONE;
|
||||
pmc_pm_data.core_osc_time = core_good_time[0];
|
||||
pmc_pm_data.core_pmu_time = core_good_time[1];
|
||||
|
||||
if (of_property_read_u32(np, "nvidia,core-pwr-off-time",
|
||||
&prop))
|
||||
suspend_mode = TEGRA_SUSPEND_NONE;
|
||||
pmc_pm_data.core_off_time = prop;
|
||||
|
||||
pmc_pm_data.corereq_high = of_property_read_bool(np,
|
||||
"nvidia,core-power-req-active-high");
|
||||
|
||||
pmc_pm_data.sysclkreq_high = of_property_read_bool(np,
|
||||
"nvidia,sys-clock-req-active-high");
|
||||
|
||||
pmc_pm_data.combined_req = of_property_read_bool(np,
|
||||
"nvidia,combined-power-req");
|
||||
|
||||
pmc_pm_data.cpu_pwr_good_en = of_property_read_bool(np,
|
||||
"nvidia,cpu-pwr-good-en");
|
||||
|
||||
if (of_property_read_u32_array(np, "nvidia,lp0-vec", lp0_vec,
|
||||
ARRAY_SIZE(lp0_vec)))
|
||||
if (suspend_mode == TEGRA_SUSPEND_LP0)
|
||||
suspend_mode = TEGRA_SUSPEND_LP1;
|
||||
|
||||
pmc_pm_data.lp0_vec_phy_addr = lp0_vec[0];
|
||||
pmc_pm_data.lp0_vec_size = lp0_vec[1];
|
||||
|
||||
pmc_pm_data.suspend_mode = suspend_mode;
|
||||
}
|
||||
|
||||
void __init tegra_pmc_init(void)
|
||||
|
|
|
|||
|
|
@ -18,6 +18,20 @@
|
|||
#ifndef __MACH_TEGRA_PMC_H
|
||||
#define __MACH_TEGRA_PMC_H
|
||||
|
||||
enum tegra_suspend_mode {
|
||||
TEGRA_SUSPEND_NONE = 0,
|
||||
TEGRA_SUSPEND_LP2, /* CPU voltage off */
|
||||
TEGRA_SUSPEND_LP1, /* CPU voltage off, DRAM self-refresh */
|
||||
TEGRA_SUSPEND_LP0, /* CPU + core voltage off, DRAM self-refresh */
|
||||
TEGRA_MAX_SUSPEND_MODE,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
|
||||
void tegra_pmc_pm_set(enum tegra_suspend_mode mode);
|
||||
void tegra_pmc_suspend_init(void);
|
||||
#endif
|
||||
|
||||
bool tegra_pmc_cpu_is_powered(int cpuid);
|
||||
int tegra_pmc_cpu_power_on(int cpuid);
|
||||
int tegra_pmc_cpu_remove_clamping(int cpuid);
|
||||
|
|
|
|||
|
|
@ -33,6 +33,8 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/i2c-tegra.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/sys_soc.h>
|
||||
#include <linux/usb/tegra_usb_phy.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
|
|
@ -42,6 +44,7 @@
|
|||
|
||||
#include "board.h"
|
||||
#include "common.h"
|
||||
#include "fuse.h"
|
||||
#include "iomap.h"
|
||||
|
||||
static struct tegra_ehci_platform_data tegra_ehci1_pdata = {
|
||||
|
|
@ -80,12 +83,36 @@ static struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
|
|||
|
||||
static void __init tegra_dt_init(void)
|
||||
{
|
||||
struct soc_device_attribute *soc_dev_attr;
|
||||
struct soc_device *soc_dev;
|
||||
struct device *parent = NULL;
|
||||
|
||||
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
|
||||
if (!soc_dev_attr)
|
||||
goto out;
|
||||
|
||||
soc_dev_attr->family = kasprintf(GFP_KERNEL, "Tegra");
|
||||
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d", tegra_revision);
|
||||
soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%d", tegra_chip_id);
|
||||
|
||||
soc_dev = soc_device_register(soc_dev_attr);
|
||||
if (IS_ERR(soc_dev)) {
|
||||
kfree(soc_dev_attr->family);
|
||||
kfree(soc_dev_attr->revision);
|
||||
kfree(soc_dev_attr->soc_id);
|
||||
kfree(soc_dev_attr);
|
||||
goto out;
|
||||
}
|
||||
|
||||
parent = soc_device_to_device(soc_dev);
|
||||
|
||||
/*
|
||||
* Finished with the static registrations now; fill in the missing
|
||||
* devices
|
||||
*/
|
||||
out:
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
tegra20_auxdata_lookup, NULL);
|
||||
tegra20_auxdata_lookup, parent);
|
||||
}
|
||||
|
||||
static void __init trimslice_init(void)
|
||||
|
|
|
|||
104
arch/arm/mach-tegra/tegra114_speedo.c
Normal file
104
arch/arm/mach-tegra/tegra114_speedo.c
Normal file
|
|
@ -0,0 +1,104 @@
|
|||
/*
|
||||
* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/bug.h>
|
||||
|
||||
#include "fuse.h"
|
||||
|
||||
#define CORE_PROCESS_CORNERS_NUM 2
|
||||
#define CPU_PROCESS_CORNERS_NUM 2
|
||||
|
||||
enum {
|
||||
THRESHOLD_INDEX_0,
|
||||
THRESHOLD_INDEX_1,
|
||||
THRESHOLD_INDEX_COUNT,
|
||||
};
|
||||
|
||||
static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
|
||||
{1123, UINT_MAX},
|
||||
{0, UINT_MAX},
|
||||
};
|
||||
|
||||
static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
|
||||
{1695, UINT_MAX},
|
||||
{0, UINT_MAX},
|
||||
};
|
||||
|
||||
static void rev_sku_to_speedo_ids(int rev, int sku, int *threshold)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
switch (sku) {
|
||||
case 0x00:
|
||||
case 0x10:
|
||||
case 0x05:
|
||||
case 0x06:
|
||||
tegra_cpu_speedo_id = 1;
|
||||
tegra_soc_speedo_id = 0;
|
||||
*threshold = THRESHOLD_INDEX_0;
|
||||
break;
|
||||
|
||||
case 0x03:
|
||||
case 0x04:
|
||||
tegra_cpu_speedo_id = 2;
|
||||
tegra_soc_speedo_id = 1;
|
||||
*threshold = THRESHOLD_INDEX_1;
|
||||
break;
|
||||
|
||||
default:
|
||||
pr_err("Tegra114 Unknown SKU %d\n", sku);
|
||||
tegra_cpu_speedo_id = 0;
|
||||
tegra_soc_speedo_id = 0;
|
||||
*threshold = THRESHOLD_INDEX_0;
|
||||
break;
|
||||
}
|
||||
|
||||
if (rev == TEGRA_REVISION_A01) {
|
||||
tmp = tegra_fuse_readl(0x270) << 1;
|
||||
tmp |= tegra_fuse_readl(0x26c);
|
||||
if (!tmp)
|
||||
tegra_cpu_speedo_id = 0;
|
||||
}
|
||||
}
|
||||
|
||||
void tegra114_init_speedo_data(void)
|
||||
{
|
||||
u32 cpu_speedo_val;
|
||||
u32 core_speedo_val;
|
||||
int threshold;
|
||||
int i;
|
||||
|
||||
BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
|
||||
THRESHOLD_INDEX_COUNT);
|
||||
BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
|
||||
THRESHOLD_INDEX_COUNT);
|
||||
|
||||
rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id, &threshold);
|
||||
|
||||
cpu_speedo_val = tegra_fuse_readl(0x12c) + 1024;
|
||||
core_speedo_val = tegra_fuse_readl(0x134);
|
||||
|
||||
for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++)
|
||||
if (cpu_speedo_val < cpu_process_speedos[threshold][i])
|
||||
break;
|
||||
tegra_cpu_process_id = i;
|
||||
|
||||
for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++)
|
||||
if (core_speedo_val < core_process_speedos[threshold][i])
|
||||
break;
|
||||
tegra_core_process_id = i;
|
||||
}
|
||||
|
|
@ -72,6 +72,7 @@ struct tegra_gpio_bank {
|
|||
u32 oe[4];
|
||||
u32 int_enb[4];
|
||||
u32 int_lvl[4];
|
||||
u32 wake_enb[4];
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
@ -333,15 +334,31 @@ static int tegra_gpio_suspend(struct device *dev)
|
|||
bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
|
||||
bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
|
||||
bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
|
||||
|
||||
/* Enable gpio irq for wake up source */
|
||||
tegra_gpio_writel(bank->wake_enb[p],
|
||||
GPIO_INT_ENB(gpio));
|
||||
}
|
||||
}
|
||||
local_irq_restore(flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
|
||||
static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
|
||||
{
|
||||
struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
|
||||
int gpio = d->hwirq;
|
||||
u32 port, bit, mask;
|
||||
|
||||
port = GPIO_PORT(gpio);
|
||||
bit = GPIO_BIT(gpio);
|
||||
mask = BIT(bit);
|
||||
|
||||
if (enable)
|
||||
bank->wake_enb[port] |= mask;
|
||||
else
|
||||
bank->wake_enb[port] &= ~mask;
|
||||
|
||||
return irq_set_irq_wake(bank->irq, enable);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -353,7 +370,7 @@ static struct irq_chip tegra_gpio_irq_chip = {
|
|||
.irq_unmask = tegra_gpio_irq_unmask,
|
||||
.irq_set_type = tegra_gpio_irq_set_type,
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
.irq_set_wake = tegra_gpio_wake_enable,
|
||||
.irq_set_wake = tegra_gpio_irq_set_wake,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue