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IIO: add DT bindings for stm32 DFSDM filter
Add bindings that describes STM32 Digital Filter for Sigma Delta Modulators. DFSDM allows to connect sigma delta modulators. Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Arnaud Pouliquen
Mark Brown
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Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt
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Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt
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STMicroelectronics STM32 DFSDM ADC device driver
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STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
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interface external sigma delta modulators to STM32 micro controllers.
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It is mainly targeted for:
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- Sigma delta modulators (motor control, metering...)
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- PDM microphones (audio digital microphone)
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It features up to 8 serial digital interfaces (SPI or Manchester) and
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up to 4 filters on stm32h7.
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Each child node match with a filter instance.
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Contents of a STM32 DFSDM root node:
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------------------------------------
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Required properties:
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- compatible: Should be "st,stm32h7-dfsdm".
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- reg: Offset and length of the DFSDM block register set.
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- clocks: IP and serial interfaces clocking. Should be set according
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to rcc clock ID and "clock-names".
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- clock-names: Input clock name "dfsdm" must be defined,
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"audio" is optional. If defined CLKOUT is based on the audio
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clock, else "dfsdm" is used.
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- #interrupt-cells = <1>;
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- #address-cells = <1>;
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- #size-cells = <0>;
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Optional properties:
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- spi-max-frequency: Requested only for SPI master mode.
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SPI clock OUT frequency (Hz). This clock must be set according
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to "clock" property. Frequency must be a multiple of the rcc
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clock frequency. If not, SPI CLKOUT frequency will not be
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accurate.
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Contents of a STM32 DFSDM child nodes:
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--------------------------------------
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Required properties:
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- compatible: Must be:
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"st,stm32-dfsdm-adc" for sigma delta ADCs
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"st,stm32-dfsdm-dmic" for audio digital microphone.
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- reg: Specifies the DFSDM filter instance used.
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- interrupts: IRQ lines connected to each DFSDM filter instance.
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- st,adc-channels: List of single-ended channels muxed for this ADC.
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valid values:
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"st,stm32h7-dfsdm" compatibility: 0 to 7.
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- st,adc-channel-names: List of single-ended channel names.
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- st,filter-order: SinC filter order from 0 to 5.
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0: FastSinC
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[1-5]: order 1 to 5.
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For audio purpose it is recommended to use order 3 to 5.
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- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers".
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Required properties for "st,stm32-dfsdm-adc" compatibility:
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- io-channels: From common IIO binding. Used to pipe external sigma delta
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modulator or internal ADC output to DFSDM channel.
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This is not required for "st,stm32-dfsdm-pdm" compatibility as
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PDM microphone is binded in Audio DT node.
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Required properties for "st,stm32-dfsdm-pdm" compatibility:
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- #sound-dai-cells: Must be set to 0.
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- dma: DMA controller phandle and DMA request line associated to the
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filter instance (specified by the field "reg")
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- dma-names: Must be "rx"
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Optional properties:
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- st,adc-channel-types: Single-ended channel input type.
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- "SPI_R": SPI with data on rising edge (default)
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- "SPI_F": SPI with data on falling edge
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- "MANCH_R": manchester codec, rising edge = logic 0
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- "MANCH_F": manchester codec, falling edge = logic 1
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- st,adc-channel-clk-src: Conversion clock source.
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- "CLKIN": external SPI clock (CLKIN x)
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- "CLKOUT": internal SPI clock (CLKOUT) (default)
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- "CLKOUT_F": internal SPI clock divided by 2 (falling edge).
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- "CLKOUT_R": internal SPI clock divided by 2 (rising edge).
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- st,adc-alt-channel: Must be defined if two sigma delta modulator are
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connected on same SPI input.
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If not set, channel n is connected to SPI input n.
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If set, channel n is connected to SPI input n + 1.
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- st,filter0-sync: Set to 1 to synchronize with DFSDM filter instance 0.
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Used for multi microphones synchronization.
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Example of a sigma delta adc connected on DFSDM SPI port 0
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and a pdm microphone connected on DFSDM SPI port 1:
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ads1202: simple_sd_adc@0 {
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compatible = "ads1202";
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#io-channel-cells = <1>;
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};
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dfsdm: dfsdm@40017000 {
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compatible = "st,stm32h7-dfsdm";
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reg = <0x40017000 0x400>;
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clocks = <&rcc DFSDM1_CK>;
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clock-names = "dfsdm";
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#interrupt-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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dfsdm_adc0: filter@0 {
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compatible = "st,stm32-dfsdm-adc";
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#io-channel-cells = <1>;
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reg = <0>;
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interrupts = <110>;
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st,adc-channels = <0>;
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st,adc-channel-names = "sd_adc0";
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st,adc-channel-types = "SPI_F";
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st,adc-channel-clk-src = "CLKOUT";
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io-channels = <&ads1202 0>;
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st,filter-order = <3>;
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};
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dfsdm_pdm1: filter@1 {
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compatible = "st,stm32-dfsdm-dmic";
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reg = <1>;
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interrupts = <111>;
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dmas = <&dmamux1 102 0x400 0x00>;
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dma-names = "rx";
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st,adc-channels = <1>;
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st,adc-channel-names = "dmic1";
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st,adc-channel-types = "SPI_R";
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st,adc-channel-clk-src = "CLKOUT";
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st,filter-order = <5>;
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};
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}
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