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powerpc/sysdev: Add __init attribute to eligible functions
Some files functions in 'arch/powerpc/sysdev' are deserving of an `__init` macro attribute. These functions are only called by other initialization functions and therefore should inherit the attribute. Also, change function declarations in header files to include `__init`. Signed-off-by: Nick Child <nick.child@ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20211216220035.605465-6-nick.child@ibm.com
This commit is contained in:
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c49f5d88ff
commit
6c552983d0
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@ -1133,8 +1133,8 @@ enum cpm_clk {
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CPM_CLK_DUMMY
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CPM_CLK_DUMMY
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};
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};
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extern int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode);
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int __init cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode);
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extern int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock);
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int __init cpm2_smc_clk_setup(enum cpm_clk_target target, int clock);
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#define CPM_PIN_INPUT 0
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#define CPM_PIN_INPUT 0
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#define CPM_PIN_OUTPUT 1
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#define CPM_PIN_OUTPUT 1
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@ -1143,7 +1143,7 @@ extern int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock);
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#define CPM_PIN_GPIO 4
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#define CPM_PIN_GPIO 4
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#define CPM_PIN_OPENDRAIN 8
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#define CPM_PIN_OPENDRAIN 8
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void cpm2_set_pin(int port, int pin, int flags);
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void __init cpm2_set_pin(int port, int pin, int flags);
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#endif /* __CPM2__ */
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#endif /* __CPM2__ */
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#endif /* __KERNEL__ */
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#endif /* __KERNEL__ */
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@ -7,7 +7,7 @@
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extern void i8259_init(struct device_node *node, unsigned long intack_addr);
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extern void i8259_init(struct device_node *node, unsigned long intack_addr);
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extern unsigned int i8259_irq(void);
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extern unsigned int i8259_irq(void);
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extern struct irq_domain *i8259_get_host(void);
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struct irq_domain *__init i8259_get_host(void);
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#endif /* __KERNEL__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_I8259_H */
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#endif /* _ASM_POWERPC_I8259_H */
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@ -65,7 +65,7 @@ enum ipic_mcp_irq {
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IPIC_MCP_MU = 7,
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IPIC_MCP_MU = 7,
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};
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};
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extern void ipic_set_default_priority(void);
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void __init ipic_set_default_priority(void);
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extern u32 ipic_get_mcp_status(void);
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extern u32 ipic_get_mcp_status(void);
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extern void ipic_clear_mcp_status(u32 mask);
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extern void ipic_clear_mcp_status(u32 mask);
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@ -472,7 +472,7 @@ extern int mpic_cpu_get_priority(void);
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extern void mpic_cpu_set_priority(int prio);
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extern void mpic_cpu_set_priority(int prio);
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/* Request IPIs on primary mpic */
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/* Request IPIs on primary mpic */
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extern void mpic_request_ipis(void);
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void __init mpic_request_ipis(void);
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/* Send a message (IPI) to a given target (cpu number or MSG_*) */
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/* Send a message (IPI) to a given target (cpu number or MSG_*) */
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void smp_mpic_message_pass(int target, int msg);
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void smp_mpic_message_pass(int target, int msg);
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@ -38,13 +38,13 @@ static inline int icp_native_init(void) { return -ENODEV; }
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/* PAPR ICP */
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/* PAPR ICP */
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#ifdef CONFIG_PPC_ICP_HV
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#ifdef CONFIG_PPC_ICP_HV
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extern int icp_hv_init(void);
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int __init icp_hv_init(void);
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#else
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#else
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static inline int icp_hv_init(void) { return -ENODEV; }
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static inline int icp_hv_init(void) { return -ENODEV; }
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#endif
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#endif
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#ifdef CONFIG_PPC_POWERNV
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#ifdef CONFIG_PPC_POWERNV
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extern int icp_opal_init(void);
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int __init icp_opal_init(void);
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extern void icp_opal_flush_interrupt(void);
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extern void icp_opal_flush_interrupt(void);
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#else
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#else
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static inline int icp_opal_init(void) { return -ENODEV; }
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static inline int icp_opal_init(void) { return -ENODEV; }
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@ -135,7 +135,7 @@ void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src)
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}
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}
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EXPORT_SYMBOL(__cpm2_setbrg);
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EXPORT_SYMBOL(__cpm2_setbrg);
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int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
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int __init cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
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{
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{
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int ret = 0;
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int ret = 0;
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int shift;
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int shift;
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@ -265,7 +265,7 @@ int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
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return ret;
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return ret;
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}
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}
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int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock)
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int __init cpm2_smc_clk_setup(enum cpm_clk_target target, int clock)
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{
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{
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int ret = 0;
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int ret = 0;
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int shift;
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int shift;
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@ -326,7 +326,7 @@ struct cpm2_ioports {
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u32 res[3];
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u32 res[3];
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};
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};
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void cpm2_set_pin(int port, int pin, int flags)
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void __init cpm2_set_pin(int port, int pin, int flags)
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{
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{
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struct cpm2_ioports __iomem *iop =
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struct cpm2_ioports __iomem *iop =
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(struct cpm2_ioports __iomem *)&cpm2_immr->im_ioport;
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(struct cpm2_ioports __iomem *)&cpm2_immr->im_ioport;
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@ -226,7 +226,7 @@ static void dart_free(struct iommu_table *tbl, long index, long npages)
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dart_cache_sync(orig_dp, orig_npages);
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dart_cache_sync(orig_dp, orig_npages);
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}
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}
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static void allocate_dart(void)
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static void __init allocate_dart(void)
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{
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{
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unsigned long tmp;
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unsigned long tmp;
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@ -58,7 +58,7 @@ static struct irq_chip fsl_mpic_err_chip = {
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.irq_unmask = fsl_mpic_unmask_err,
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.irq_unmask = fsl_mpic_unmask_err,
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};
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};
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int mpic_setup_error_int(struct mpic *mpic, int intvec)
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int __init mpic_setup_error_int(struct mpic *mpic, int intvec)
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{
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{
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int i;
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int i;
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@ -121,7 +121,7 @@ static irqreturn_t fsl_error_int_handler(int irq, void *data)
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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}
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}
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void mpic_err_int_init(struct mpic *mpic, irq_hw_number_t irqnum)
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void __init mpic_err_int_init(struct mpic *mpic, irq_hw_number_t irqnum)
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{
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{
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unsigned int virq;
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unsigned int virq;
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int ret;
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int ret;
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@ -1106,7 +1106,7 @@ static const struct of_device_id pci_ids[] = {
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struct device_node *fsl_pci_primary;
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struct device_node *fsl_pci_primary;
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void fsl_pci_assign_primary(void)
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void __init fsl_pci_assign_primary(void)
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{
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{
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struct device_node *np;
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struct device_node *np;
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@ -120,7 +120,7 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose);
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extern struct device_node *fsl_pci_primary;
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extern struct device_node *fsl_pci_primary;
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#ifdef CONFIG_PCI
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#ifdef CONFIG_PCI
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void fsl_pci_assign_primary(void);
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void __init fsl_pci_assign_primary(void);
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#else
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#else
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static inline void fsl_pci_assign_primary(void) {}
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static inline void fsl_pci_assign_primary(void) {}
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#endif
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#endif
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@ -208,7 +208,7 @@ static const struct irq_domain_ops i8259_host_ops = {
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.xlate = i8259_host_xlate,
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.xlate = i8259_host_xlate,
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};
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};
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struct irq_domain *i8259_get_host(void)
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struct irq_domain *__init i8259_get_host(void)
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{
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{
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return i8259_host;
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return i8259_host;
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}
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}
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@ -767,7 +767,7 @@ struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
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return ipic;
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return ipic;
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}
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}
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void ipic_set_default_priority(void)
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void __init ipic_set_default_priority(void)
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{
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{
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ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_PRIORITY_DEFAULT);
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ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_PRIORITY_DEFAULT);
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ipic_write(primary_ipic->regs, IPIC_SIPRR_B, IPIC_PRIORITY_DEFAULT);
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ipic_write(primary_ipic->regs, IPIC_SIPRR_B, IPIC_PRIORITY_DEFAULT);
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@ -1839,7 +1839,7 @@ unsigned int mpic_get_mcirq(void)
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}
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}
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#ifdef CONFIG_SMP
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#ifdef CONFIG_SMP
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void mpic_request_ipis(void)
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void __init mpic_request_ipis(void)
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{
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{
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struct mpic *mpic = mpic_primary;
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struct mpic *mpic = mpic_primary;
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int i;
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int i;
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@ -8,8 +8,8 @@
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#ifdef CONFIG_PCI_MSI
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#ifdef CONFIG_PCI_MSI
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extern void mpic_msi_reserve_hwirq(struct mpic *mpic, irq_hw_number_t hwirq);
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extern void mpic_msi_reserve_hwirq(struct mpic *mpic, irq_hw_number_t hwirq);
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extern int mpic_msi_init_allocator(struct mpic *mpic);
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int __init mpic_msi_init_allocator(struct mpic *mpic);
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extern int mpic_u3msi_init(struct mpic *mpic);
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int __init mpic_u3msi_init(struct mpic *mpic);
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#else
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#else
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static inline void mpic_msi_reserve_hwirq(struct mpic *mpic,
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static inline void mpic_msi_reserve_hwirq(struct mpic *mpic,
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irq_hw_number_t hwirq)
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irq_hw_number_t hwirq)
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@ -37,8 +37,8 @@ extern void mpic_reset_core(int cpu);
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#ifdef CONFIG_FSL_SOC
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#ifdef CONFIG_FSL_SOC
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extern int mpic_map_error_int(struct mpic *mpic, unsigned int virq, irq_hw_number_t hw);
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extern int mpic_map_error_int(struct mpic *mpic, unsigned int virq, irq_hw_number_t hw);
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extern void mpic_err_int_init(struct mpic *mpic, irq_hw_number_t irqnum);
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void __init mpic_err_int_init(struct mpic *mpic, irq_hw_number_t irqnum);
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extern int mpic_setup_error_int(struct mpic *mpic, int intvec);
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int __init mpic_setup_error_int(struct mpic *mpic, int intvec);
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#else
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#else
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static inline int mpic_map_error_int(struct mpic *mpic, unsigned int virq, irq_hw_number_t hw)
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static inline int mpic_map_error_int(struct mpic *mpic, unsigned int virq, irq_hw_number_t hw)
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{
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{
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@ -24,7 +24,7 @@ void mpic_msi_reserve_hwirq(struct mpic *mpic, irq_hw_number_t hwirq)
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}
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}
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#ifdef CONFIG_MPIC_U3_HT_IRQS
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#ifdef CONFIG_MPIC_U3_HT_IRQS
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static int mpic_msi_reserve_u3_hwirqs(struct mpic *mpic)
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static int __init mpic_msi_reserve_u3_hwirqs(struct mpic *mpic)
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{
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{
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irq_hw_number_t hwirq;
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irq_hw_number_t hwirq;
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const struct irq_domain_ops *ops = mpic->irqhost->ops;
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const struct irq_domain_ops *ops = mpic->irqhost->ops;
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@ -68,13 +68,13 @@ static int mpic_msi_reserve_u3_hwirqs(struct mpic *mpic)
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return 0;
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return 0;
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}
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}
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#else
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#else
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static int mpic_msi_reserve_u3_hwirqs(struct mpic *mpic)
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static int __init mpic_msi_reserve_u3_hwirqs(struct mpic *mpic)
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{
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{
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return -1;
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return -1;
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}
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}
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#endif
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#endif
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int mpic_msi_init_allocator(struct mpic *mpic)
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int __init mpic_msi_init_allocator(struct mpic *mpic)
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{
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{
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int rc;
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int rc;
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@ -384,7 +384,7 @@ struct mpic_timer *mpic_request_timer(irq_handler_t fn, void *dev,
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}
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}
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EXPORT_SYMBOL(mpic_request_timer);
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EXPORT_SYMBOL(mpic_request_timer);
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static int timer_group_get_freq(struct device_node *np,
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static int __init timer_group_get_freq(struct device_node *np,
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struct timer_group_priv *priv)
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struct timer_group_priv *priv)
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{
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{
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u32 div;
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u32 div;
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@ -411,7 +411,7 @@ static int timer_group_get_freq(struct device_node *np,
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return 0;
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return 0;
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}
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}
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static int timer_group_get_irq(struct device_node *np,
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static int __init timer_group_get_irq(struct device_node *np,
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struct timer_group_priv *priv)
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struct timer_group_priv *priv)
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{
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{
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const u32 all_timer[] = { 0, TIMERS_PER_GROUP };
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const u32 all_timer[] = { 0, TIMERS_PER_GROUP };
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@ -459,7 +459,7 @@ static int timer_group_get_irq(struct device_node *np,
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return 0;
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return 0;
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}
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}
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static void timer_group_init(struct device_node *np)
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static void __init timer_group_init(struct device_node *np)
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{
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{
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struct timer_group_priv *priv;
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struct timer_group_priv *priv;
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unsigned int i = 0;
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unsigned int i = 0;
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@ -174,7 +174,7 @@ static int u3msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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return 0;
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return 0;
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}
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}
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int mpic_u3msi_init(struct mpic *mpic)
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int __init mpic_u3msi_init(struct mpic *mpic)
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{
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{
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int rc;
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int rc;
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struct pci_controller *phb;
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struct pci_controller *phb;
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@ -257,7 +257,7 @@ static void tsi108_pci_int_unmask(u_int irq)
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mb();
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mb();
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}
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}
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static void init_pci_source(void)
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static void __init init_pci_source(void)
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{
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{
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tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL,
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tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL,
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0x0000ff00);
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0x0000ff00);
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@ -92,7 +92,7 @@ int memcons_getc(void)
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return c;
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return c;
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}
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}
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void udbg_init_memcons(void)
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void __init udbg_init_memcons(void)
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{
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{
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udbg_putc = memcons_putc;
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udbg_putc = memcons_putc;
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udbg_getc = memcons_getc;
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udbg_getc = memcons_getc;
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@ -162,7 +162,7 @@ static const struct icp_ops icp_hv_ops = {
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#endif
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#endif
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};
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};
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int icp_hv_init(void)
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int __init icp_hv_init(void)
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{
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{
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struct device_node *np;
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struct device_node *np;
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@ -184,7 +184,7 @@ static const struct icp_ops icp_opal_ops = {
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#endif
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#endif
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};
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};
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int icp_opal_init(void)
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int __init icp_opal_init(void)
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{
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{
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struct device_node *np;
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struct device_node *np;
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@ -121,7 +121,7 @@ void xics_mask_unknown_vec(unsigned int vec)
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#ifdef CONFIG_SMP
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#ifdef CONFIG_SMP
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static void xics_request_ipi(void)
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static void __init xics_request_ipi(void)
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{
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{
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unsigned int ipi;
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unsigned int ipi;
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@ -492,7 +492,7 @@ static const struct xive_ops xive_native_ops = {
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.name = "native",
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.name = "native",
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};
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};
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static bool xive_parse_provisioning(struct device_node *np)
|
static bool __init xive_parse_provisioning(struct device_node *np)
|
||||||
{
|
{
|
||||||
int rc;
|
int rc;
|
||||||
|
|
||||||
|
@ -532,7 +532,7 @@ static bool xive_parse_provisioning(struct device_node *np)
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void xive_native_setup_pools(void)
|
static void __init xive_native_setup_pools(void)
|
||||||
{
|
{
|
||||||
/* Allocate a pool big enough */
|
/* Allocate a pool big enough */
|
||||||
pr_debug("XIVE: Allocating VP block for pool size %u\n", nr_cpu_ids);
|
pr_debug("XIVE: Allocating VP block for pool size %u\n", nr_cpu_ids);
|
||||||
|
|
|
@ -44,7 +44,7 @@ struct xive_irq_bitmap {
|
||||||
|
|
||||||
static LIST_HEAD(xive_irq_bitmaps);
|
static LIST_HEAD(xive_irq_bitmaps);
|
||||||
|
|
||||||
static int xive_irq_bitmap_add(int base, int count)
|
static int __init xive_irq_bitmap_add(int base, int count)
|
||||||
{
|
{
|
||||||
struct xive_irq_bitmap *xibm;
|
struct xive_irq_bitmap *xibm;
|
||||||
|
|
||||||
|
@ -687,7 +687,7 @@ static const struct xive_ops xive_spapr_ops = {
|
||||||
/*
|
/*
|
||||||
* get max priority from "/ibm,plat-res-int-priorities"
|
* get max priority from "/ibm,plat-res-int-priorities"
|
||||||
*/
|
*/
|
||||||
static bool xive_get_max_prio(u8 *max_prio)
|
static bool __init xive_get_max_prio(u8 *max_prio)
|
||||||
{
|
{
|
||||||
struct device_node *rootdn;
|
struct device_node *rootdn;
|
||||||
const __be32 *reg;
|
const __be32 *reg;
|
||||||
|
@ -741,7 +741,7 @@ static bool xive_get_max_prio(u8 *max_prio)
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
static const u8 *get_vec5_feature(unsigned int index)
|
static const u8 *__init get_vec5_feature(unsigned int index)
|
||||||
{
|
{
|
||||||
unsigned long root, chosen;
|
unsigned long root, chosen;
|
||||||
int size;
|
int size;
|
||||||
|
|
Loading…
Reference in a new issue