mirror of
https://github.com/torvalds/linux
synced 2024-10-27 13:48:49 +00:00
staging: brcm80211: removed 32 bit DMA functions
Code cleanup. Removed unused functions. Signed-off-by: Roland Vossen <rvossen@broadcom.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Roland Vossen
Greg Kroah-Hartman
parent
36e319bd39
commit
6b4ba667b7
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@ -213,28 +213,6 @@ static void *dma_ringalloc(struct osl_info *osh, u32 boundary, uint size,
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u16 *alignbits, uint *alloced,
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dmaaddr_t *descpa, osldma_t **dmah);
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/* Prototypes for 32-bit routines */
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static bool dma32_alloc(dma_info_t *di, uint direction);
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static bool dma32_txreset(dma_info_t *di);
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static bool dma32_rxreset(dma_info_t *di);
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static bool dma32_txsuspendedidle(dma_info_t *di);
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static int dma32_txfast(dma_info_t *di, struct sk_buff *p0, bool commit);
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static void *dma32_getnexttxp(dma_info_t *di, txd_range_t range);
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static void *dma32_getnextrxp(dma_info_t *di, bool forceall);
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static void dma32_txrotate(dma_info_t *di);
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static bool dma32_rxidle(dma_info_t *di);
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static void dma32_txinit(dma_info_t *di);
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static bool dma32_txenabled(dma_info_t *di);
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static void dma32_txsuspend(dma_info_t *di);
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static void dma32_txresume(dma_info_t *di);
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static bool dma32_txsuspended(dma_info_t *di);
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static void dma32_txreclaim(dma_info_t *di, txd_range_t range);
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static bool dma32_txstopped(dma_info_t *di);
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static bool dma32_rxstopped(dma_info_t *di);
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static bool dma32_rxenabled(dma_info_t *di);
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static bool _dma32_addrext(struct osl_info *osh, dma32regs_t *dma32regs);
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/* Prototypes for 64-bit routines */
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static bool dma64_alloc(dma_info_t *di, uint direction);
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static bool dma64_txreset(dma_info_t *di);
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@ -308,53 +286,6 @@ const di_fcn_t dma64proc = {
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39
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};
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static const di_fcn_t dma32proc = {
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(di_detach_t) _dma_detach,
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(di_txinit_t) dma32_txinit,
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(di_txreset_t) dma32_txreset,
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(di_txenabled_t) dma32_txenabled,
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(di_txsuspend_t) dma32_txsuspend,
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(di_txresume_t) dma32_txresume,
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(di_txsuspended_t) dma32_txsuspended,
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(di_txsuspendedidle_t) dma32_txsuspendedidle,
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(di_txfast_t) dma32_txfast,
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NULL,
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NULL,
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(di_txstopped_t) dma32_txstopped,
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(di_txreclaim_t) dma32_txreclaim,
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(di_getnexttxp_t) dma32_getnexttxp,
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(di_peeknexttxp_t) _dma_peeknexttxp,
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(di_txblock_t) _dma_txblock,
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(di_txunblock_t) _dma_txunblock,
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(di_txactive_t) _dma_txactive,
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(di_txrotate_t) dma32_txrotate,
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(di_rxinit_t) _dma_rxinit,
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(di_rxreset_t) dma32_rxreset,
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(di_rxidle_t) dma32_rxidle,
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(di_rxstopped_t) dma32_rxstopped,
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(di_rxenable_t) _dma_rxenable,
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(di_rxenabled_t) dma32_rxenabled,
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(di_rx_t) _dma_rx,
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(di_rxfill_t) _dma_rxfill,
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(di_rxreclaim_t) _dma_rxreclaim,
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(di_getnextrxp_t) _dma_getnextrxp,
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(di_peeknextrxp_t) _dma_peeknextrxp,
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(di_rxparam_get_t) _dma_rx_param_get,
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(di_fifoloopbackenable_t) _dma_fifoloopbackenable,
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(di_getvar_t) _dma_getvar,
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(di_counterreset_t) _dma_counterreset,
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(di_ctrlflags_t) _dma_ctrlflags,
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NULL,
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NULL,
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NULL,
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(di_rxactive_t) _dma_rxactive,
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(di_txpending_t) _dma_txpending,
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(di_txcommitted_t) _dma_txcommitted,
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39
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};
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struct hnddma_pub *dma_attach(struct osl_info *osh, char *name, si_t *sih,
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void *dmaregstx, void *dmaregsrx, uint ntxd,
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uint nrxd, uint rxbufsize, int rxextheadroom,
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@ -543,32 +474,6 @@ struct hnddma_pub *dma_attach(struct osl_info *osh, char *name, si_t *sih,
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return NULL;
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}
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/* init the tx or rx descriptor */
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static inline void
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dma32_dd_upd(dma_info_t *di, dma32dd_t *ddring, dmaaddr_t pa, uint outidx,
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u32 *flags, u32 bufcount)
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{
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/* dma32 uses 32-bit control to fit both flags and bufcounter */
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*flags = *flags | (bufcount & CTRL_BC_MASK);
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if ((di->dataoffsetlow == 0) || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) {
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W_SM(&ddring[outidx].addr,
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BUS_SWAP32(PHYSADDRLO(pa) + di->dataoffsetlow));
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W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*flags));
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} else {
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/* address extension */
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u32 ae;
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ASSERT(di->addrext);
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ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
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PHYSADDRLO(pa) &= ~PCI32ADDR_HIGH;
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*flags |= (ae << CTRL_AE_SHIFT);
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W_SM(&ddring[outidx].addr,
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BUS_SWAP32(PHYSADDRLO(pa) + di->dataoffsetlow));
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W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*flags));
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}
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}
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/* Check for odd number of 1's */
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static inline u32 parity32(u32 data)
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{
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@ -629,16 +534,6 @@ dma64_dd_upd(dma_info_t *di, dma64dd_t *ddring, dmaaddr_t pa, uint outidx,
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}
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}
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static bool _dma32_addrext(struct osl_info *osh, dma32regs_t *dma32regs)
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{
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u32 w;
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OR_REG(osh, &dma32regs->control, XC_AE);
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w = R_REG(osh, &dma32regs->control);
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AND_REG(osh, &dma32regs->control, ~XC_AE);
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return (w & XC_AE) == XC_AE;
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}
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static bool _dma_alloc(dma_info_t *di, uint direction)
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{
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return dma64_alloc(di, direction);
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@ -1171,11 +1066,6 @@ static unsigned long _dma_getvar(dma_info_t *di, const char *name)
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return 0;
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}
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void dma_txpioloopback(struct osl_info *osh, dma32regs_t *regs)
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{
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OR_REG(osh, ®s->control, XC_LE);
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}
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static
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u8 dma_align_sizetobits(uint size)
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{
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@ -1218,562 +1108,6 @@ static void *dma_ringalloc(struct osl_info *osh, u32 boundary, uint size,
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return va;
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}
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/* 32-bit DMA functions */
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static void dma32_txinit(dma_info_t *di)
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{
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u32 control = XC_XE;
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DMA_TRACE(("%s: dma_txinit\n", di->name));
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if (di->ntxd == 0)
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return;
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di->txin = di->txout = 0;
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di->hnddma.txavail = di->ntxd - 1;
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/* clear tx descriptor ring */
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memset((void *)di->txd32, '\0', (di->ntxd * sizeof(dma32dd_t)));
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if ((di->hnddma.dmactrlflags & DMA_CTRL_PEN) == 0)
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control |= XC_PD;
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W_REG(di->osh, &di->d32txregs->control, control);
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_dma_ddtable_init(di, DMA_TX, di->txdpa);
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}
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static bool dma32_txenabled(dma_info_t *di)
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{
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u32 xc;
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/* If the chip is dead, it is not enabled :-) */
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xc = R_REG(di->osh, &di->d32txregs->control);
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return (xc != 0xffffffff) && (xc & XC_XE);
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}
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static void dma32_txsuspend(dma_info_t *di)
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{
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DMA_TRACE(("%s: dma_txsuspend\n", di->name));
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if (di->ntxd == 0)
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return;
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OR_REG(di->osh, &di->d32txregs->control, XC_SE);
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}
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static void dma32_txresume(dma_info_t *di)
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{
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DMA_TRACE(("%s: dma_txresume\n", di->name));
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if (di->ntxd == 0)
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return;
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AND_REG(di->osh, &di->d32txregs->control, ~XC_SE);
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}
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static bool dma32_txsuspended(dma_info_t *di)
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{
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return (di->ntxd == 0)
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|| ((R_REG(di->osh, &di->d32txregs->control) & XC_SE) == XC_SE);
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}
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static void dma32_txreclaim(dma_info_t *di, txd_range_t range)
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{
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void *p;
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DMA_TRACE(("%s: dma_txreclaim %s\n", di->name,
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(range == HNDDMA_RANGE_ALL) ? "all" :
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((range ==
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HNDDMA_RANGE_TRANSMITTED) ? "transmitted" :
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"transfered")));
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if (di->txin == di->txout)
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return;
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while ((p = dma32_getnexttxp(di, range)))
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pkt_buf_free_skb(di->osh, p, true);
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}
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static bool dma32_txstopped(dma_info_t *di)
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{
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return ((R_REG(di->osh, &di->d32txregs->status) & XS_XS_MASK) ==
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XS_XS_STOPPED);
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}
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static bool dma32_rxstopped(dma_info_t *di)
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{
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return ((R_REG(di->osh, &di->d32rxregs->status) & RS_RS_MASK) ==
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RS_RS_STOPPED);
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}
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static bool dma32_alloc(dma_info_t *di, uint direction)
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{
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uint size;
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uint ddlen;
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void *va;
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uint alloced;
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u16 align;
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u16 align_bits;
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ddlen = sizeof(dma32dd_t);
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size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
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alloced = 0;
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align_bits = di->dmadesc_align;
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align = (1 << align_bits);
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if (direction == DMA_TX) {
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va = dma_ringalloc(di->osh, D32RINGALIGN, size, &align_bits,
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&alloced, &di->txdpaorig, &di->tx_dmah);
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if (va == NULL) {
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DMA_ERROR(("%s: dma_alloc: DMA_ALLOC_CONSISTENT(ntxd) failed\n", di->name));
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return false;
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}
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PHYSADDRHISET(di->txdpa, 0);
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ASSERT(PHYSADDRHI(di->txdpaorig) == 0);
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di->txd32 = (dma32dd_t *) roundup((unsigned long)va, align);
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di->txdalign =
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(uint) ((s8 *)di->txd32 - (s8 *) va);
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PHYSADDRLOSET(di->txdpa,
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PHYSADDRLO(di->txdpaorig) + di->txdalign);
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/* Make sure that alignment didn't overflow */
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ASSERT(PHYSADDRLO(di->txdpa) >= PHYSADDRLO(di->txdpaorig));
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di->txdalloc = alloced;
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ASSERT(IS_ALIGNED((unsigned long)di->txd32, align));
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} else {
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va = dma_ringalloc(di->osh, D32RINGALIGN, size, &align_bits,
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&alloced, &di->rxdpaorig, &di->rx_dmah);
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if (va == NULL) {
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DMA_ERROR(("%s: dma_alloc: DMA_ALLOC_CONSISTENT(nrxd) failed\n", di->name));
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return false;
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}
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PHYSADDRHISET(di->rxdpa, 0);
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ASSERT(PHYSADDRHI(di->rxdpaorig) == 0);
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di->rxd32 = (dma32dd_t *) roundup((unsigned long)va, align);
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di->rxdalign =
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(uint) ((s8 *)di->rxd32 - (s8 *) va);
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PHYSADDRLOSET(di->rxdpa,
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PHYSADDRLO(di->rxdpaorig) + di->rxdalign);
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/* Make sure that alignment didn't overflow */
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ASSERT(PHYSADDRLO(di->rxdpa) >= PHYSADDRLO(di->rxdpaorig));
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di->rxdalloc = alloced;
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ASSERT(IS_ALIGNED((unsigned long)di->rxd32, align));
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}
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return true;
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}
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static bool dma32_txreset(dma_info_t *di)
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{
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u32 status;
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if (di->ntxd == 0)
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return true;
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/* suspend tx DMA first */
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W_REG(di->osh, &di->d32txregs->control, XC_SE);
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SPINWAIT(((status =
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(R_REG(di->osh, &di->d32txregs->status) & XS_XS_MASK))
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!= XS_XS_DISABLED) && (status != XS_XS_IDLE)
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&& (status != XS_XS_STOPPED), (10000));
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W_REG(di->osh, &di->d32txregs->control, 0);
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SPINWAIT(((status = (R_REG(di->osh,
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&di->d32txregs->status) & XS_XS_MASK)) !=
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XS_XS_DISABLED), 10000);
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/* wait for the last transaction to complete */
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udelay(300);
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return status == XS_XS_DISABLED;
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}
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static bool dma32_rxidle(dma_info_t *di)
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{
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DMA_TRACE(("%s: dma_rxidle\n", di->name));
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if (di->nrxd == 0)
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return true;
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return ((R_REG(di->osh, &di->d32rxregs->status) & RS_CD_MASK) ==
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R_REG(di->osh, &di->d32rxregs->ptr));
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}
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static bool dma32_rxreset(dma_info_t *di)
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{
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u32 status;
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if (di->nrxd == 0)
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return true;
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W_REG(di->osh, &di->d32rxregs->control, 0);
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SPINWAIT(((status = (R_REG(di->osh,
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&di->d32rxregs->status) & RS_RS_MASK)) !=
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RS_RS_DISABLED), 10000);
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return status == RS_RS_DISABLED;
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}
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static bool dma32_rxenabled(dma_info_t *di)
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{
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u32 rc;
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rc = R_REG(di->osh, &di->d32rxregs->control);
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return (rc != 0xffffffff) && (rc & RC_RE);
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}
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static bool dma32_txsuspendedidle(dma_info_t *di)
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{
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if (di->ntxd == 0)
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return true;
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if (!(R_REG(di->osh, &di->d32txregs->control) & XC_SE))
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return 0;
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if ((R_REG(di->osh, &di->d32txregs->status) & XS_XS_MASK) != XS_XS_IDLE)
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return 0;
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udelay(2);
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return ((R_REG(di->osh, &di->d32txregs->status) & XS_XS_MASK) ==
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XS_XS_IDLE);
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}
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/* !! tx entry routine
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* supports full 32bit dma engine buffer addressing so
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* dma buffers can cross 4 Kbyte page boundaries.
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*
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* WARNING: call must check the return value for error.
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* the error(toss frames) could be fatal and cause many subsequent hard to debug problems
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*/
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static int dma32_txfast(dma_info_t *di, struct sk_buff *p0, bool commit)
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{
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struct sk_buff *p, *next;
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unsigned char *data;
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uint len;
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u16 txout;
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u32 flags = 0;
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dmaaddr_t pa;
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DMA_TRACE(("%s: dma_txfast\n", di->name));
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txout = di->txout;
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/*
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* Walk the chain of packet buffers
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* allocating and initializing transmit descriptor entries.
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*/
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for (p = p0; p; p = next) {
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uint nsegs, j;
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hnddma_seg_map_t *map;
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data = p->data;
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len = p->len;
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#ifdef BCM_DMAPAD
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len += PKTDMAPAD(di->osh, p);
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#endif
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next = p->next;
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/* return nonzero if out of tx descriptors */
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if (NEXTTXD(txout) == di->txin)
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goto outoftxd;
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if (len == 0)
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continue;
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if (DMASGLIST_ENAB)
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memset(&di->txp_dmah[txout], 0,
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sizeof(hnddma_seg_map_t));
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/* get physical address of buffer start */
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pa = DMA_MAP(di->osh, data, len, DMA_TX, p,
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&di->txp_dmah[txout]);
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if (DMASGLIST_ENAB) {
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map = &di->txp_dmah[txout];
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/* See if all the segments can be accounted for */
|
||||
if (map->nsegs >
|
||||
(uint) (di->ntxd - NTXDACTIVE(di->txin, di->txout) -
|
||||
1))
|
||||
goto outoftxd;
|
||||
|
||||
nsegs = map->nsegs;
|
||||
} else
|
||||
nsegs = 1;
|
||||
|
||||
for (j = 1; j <= nsegs; j++) {
|
||||
flags = 0;
|
||||
if (p == p0 && j == 1)
|
||||
flags |= CTRL_SOF;
|
||||
|
||||
/* With a DMA segment list, Descriptor table is filled
|
||||
* using the segment list instead of looping over
|
||||
* buffers in multi-chain DMA. Therefore, EOF for SGLIST is when
|
||||
* end of segment list is reached.
|
||||
*/
|
||||
if ((!DMASGLIST_ENAB && next == NULL) ||
|
||||
(DMASGLIST_ENAB && j == nsegs))
|
||||
flags |= (CTRL_IOC | CTRL_EOF);
|
||||
if (txout == (di->ntxd - 1))
|
||||
flags |= CTRL_EOT;
|
||||
|
||||
if (DMASGLIST_ENAB) {
|
||||
len = map->segs[j - 1].length;
|
||||
pa = map->segs[j - 1].addr;
|
||||
}
|
||||
ASSERT(PHYSADDRHI(pa) == 0);
|
||||
|
||||
dma32_dd_upd(di, di->txd32, pa, txout, &flags, len);
|
||||
ASSERT(di->txp[txout] == NULL);
|
||||
|
||||
txout = NEXTTXD(txout);
|
||||
}
|
||||
|
||||
/* See above. No need to loop over individual buffers */
|
||||
if (DMASGLIST_ENAB)
|
||||
break;
|
||||
}
|
||||
|
||||
/* if last txd eof not set, fix it */
|
||||
if (!(flags & CTRL_EOF))
|
||||
W_SM(&di->txd32[PREVTXD(txout)].ctrl,
|
||||
BUS_SWAP32(flags | CTRL_IOC | CTRL_EOF));
|
||||
|
||||
/* save the packet */
|
||||
di->txp[PREVTXD(txout)] = p0;
|
||||
|
||||
/* bump the tx descriptor index */
|
||||
di->txout = txout;
|
||||
|
||||
/* kick the chip */
|
||||
if (commit)
|
||||
W_REG(di->osh, &di->d32txregs->ptr, I2B(txout, dma32dd_t));
|
||||
|
||||
/* tx flow control */
|
||||
di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
|
||||
|
||||
return 0;
|
||||
|
||||
outoftxd:
|
||||
DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
|
||||
pkt_buf_free_skb(di->osh, p0, true);
|
||||
di->hnddma.txavail = 0;
|
||||
di->hnddma.txnobuf++;
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Reclaim next completed txd (txds if using chained buffers) in the range
|
||||
* specified and return associated packet.
|
||||
* If range is HNDDMA_RANGE_TRANSMITTED, reclaim descriptors that have be
|
||||
* transmitted as noted by the hardware "CurrDescr" pointer.
|
||||
* If range is HNDDMA_RANGE_TRANSFERED, reclaim descriptors that have be
|
||||
* transfered by the DMA as noted by the hardware "ActiveDescr" pointer.
|
||||
* If range is HNDDMA_RANGE_ALL, reclaim all txd(s) posted to the ring and
|
||||
* return associated packet regardless of the value of hardware pointers.
|
||||
*/
|
||||
static void *dma32_getnexttxp(dma_info_t *di, txd_range_t range)
|
||||
{
|
||||
u16 start, end, i;
|
||||
u16 active_desc;
|
||||
void *txp;
|
||||
|
||||
DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name,
|
||||
(range == HNDDMA_RANGE_ALL) ? "all" :
|
||||
((range ==
|
||||
HNDDMA_RANGE_TRANSMITTED) ? "transmitted" :
|
||||
"transfered")));
|
||||
|
||||
if (di->ntxd == 0)
|
||||
return NULL;
|
||||
|
||||
txp = NULL;
|
||||
|
||||
start = di->txin;
|
||||
if (range == HNDDMA_RANGE_ALL)
|
||||
end = di->txout;
|
||||
else {
|
||||
dma32regs_t *dregs = di->d32txregs;
|
||||
|
||||
end =
|
||||
(u16) B2I(R_REG(di->osh, &dregs->status) & XS_CD_MASK,
|
||||
dma32dd_t);
|
||||
|
||||
if (range == HNDDMA_RANGE_TRANSFERED) {
|
||||
active_desc =
|
||||
(u16) ((R_REG(di->osh, &dregs->status) &
|
||||
XS_AD_MASK) >> XS_AD_SHIFT);
|
||||
active_desc = (u16) B2I(active_desc, dma32dd_t);
|
||||
if (end != active_desc)
|
||||
end = PREVTXD(active_desc);
|
||||
}
|
||||
}
|
||||
|
||||
if ((start == 0) && (end > di->txout))
|
||||
goto bogus;
|
||||
|
||||
for (i = start; i != end && !txp; i = NEXTTXD(i)) {
|
||||
dmaaddr_t pa;
|
||||
hnddma_seg_map_t *map = NULL;
|
||||
uint size, j, nsegs;
|
||||
|
||||
PHYSADDRLOSET(pa,
|
||||
(BUS_SWAP32(R_SM(&di->txd32[i].addr)) -
|
||||
di->dataoffsetlow));
|
||||
PHYSADDRHISET(pa, 0);
|
||||
|
||||
if (DMASGLIST_ENAB) {
|
||||
map = &di->txp_dmah[i];
|
||||
size = map->origsize;
|
||||
nsegs = map->nsegs;
|
||||
} else {
|
||||
size =
|
||||
(BUS_SWAP32(R_SM(&di->txd32[i].ctrl)) &
|
||||
CTRL_BC_MASK);
|
||||
nsegs = 1;
|
||||
}
|
||||
|
||||
for (j = nsegs; j > 0; j--) {
|
||||
W_SM(&di->txd32[i].addr, 0xdeadbeef);
|
||||
|
||||
txp = di->txp[i];
|
||||
di->txp[i] = NULL;
|
||||
if (j > 1)
|
||||
i = NEXTTXD(i);
|
||||
}
|
||||
|
||||
DMA_UNMAP(di->osh, pa, size, DMA_TX, txp, map);
|
||||
}
|
||||
|
||||
di->txin = i;
|
||||
|
||||
/* tx flow control */
|
||||
di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
|
||||
|
||||
return txp;
|
||||
|
||||
bogus:
|
||||
DMA_NONE(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n", start, end, di->txout, forceall));
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void *dma32_getnextrxp(dma_info_t *di, bool forceall)
|
||||
{
|
||||
uint i, curr;
|
||||
void *rxp;
|
||||
dmaaddr_t pa;
|
||||
/* if forcing, dma engine must be disabled */
|
||||
ASSERT(!forceall || !dma32_rxenabled(di));
|
||||
|
||||
i = di->rxin;
|
||||
|
||||
/* return if no packets posted */
|
||||
if (i == di->rxout)
|
||||
return NULL;
|
||||
|
||||
curr =
|
||||
B2I(R_REG(di->osh, &di->d32rxregs->status) & RS_CD_MASK, dma32dd_t);
|
||||
|
||||
/* ignore curr if forceall */
|
||||
if (!forceall && (i == curr))
|
||||
return NULL;
|
||||
|
||||
/* get the packet pointer that corresponds to the rx descriptor */
|
||||
rxp = di->rxp[i];
|
||||
ASSERT(rxp);
|
||||
di->rxp[i] = NULL;
|
||||
|
||||
PHYSADDRLOSET(pa,
|
||||
(BUS_SWAP32(R_SM(&di->rxd32[i].addr)) -
|
||||
di->dataoffsetlow));
|
||||
PHYSADDRHISET(pa, 0);
|
||||
|
||||
/* clear this packet from the descriptor ring */
|
||||
DMA_UNMAP(di->osh, pa, di->rxbufsize, DMA_RX, rxp, &di->rxp_dmah[i]);
|
||||
|
||||
W_SM(&di->rxd32[i].addr, 0xdeadbeef);
|
||||
|
||||
di->rxin = NEXTRXD(i);
|
||||
|
||||
return rxp;
|
||||
}
|
||||
|
||||
/*
|
||||
* Rotate all active tx dma ring entries "forward" by (ActiveDescriptor - txin).
|
||||
*/
|
||||
static void dma32_txrotate(dma_info_t *di)
|
||||
{
|
||||
u16 ad;
|
||||
uint nactive;
|
||||
uint rot;
|
||||
u16 old, new;
|
||||
u32 w;
|
||||
u16 first, last;
|
||||
|
||||
ASSERT(dma32_txsuspendedidle(di));
|
||||
|
||||
nactive = _dma_txactive(di);
|
||||
ad = (u16) (B2I
|
||||
(((R_REG(di->osh, &di->d32txregs->status) & XS_AD_MASK)
|
||||
>> XS_AD_SHIFT), dma32dd_t));
|
||||
rot = TXD(ad - di->txin);
|
||||
|
||||
ASSERT(rot < di->ntxd);
|
||||
|
||||
/* full-ring case is a lot harder - don't worry about this */
|
||||
if (rot >= (di->ntxd - nactive)) {
|
||||
DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
|
||||
return;
|
||||
}
|
||||
|
||||
first = di->txin;
|
||||
last = PREVTXD(di->txout);
|
||||
|
||||
/* move entries starting at last and moving backwards to first */
|
||||
for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
|
||||
new = TXD(old + rot);
|
||||
|
||||
/*
|
||||
* Move the tx dma descriptor.
|
||||
* EOT is set only in the last entry in the ring.
|
||||
*/
|
||||
w = BUS_SWAP32(R_SM(&di->txd32[old].ctrl)) & ~CTRL_EOT;
|
||||
if (new == (di->ntxd - 1))
|
||||
w |= CTRL_EOT;
|
||||
W_SM(&di->txd32[new].ctrl, BUS_SWAP32(w));
|
||||
W_SM(&di->txd32[new].addr, R_SM(&di->txd32[old].addr));
|
||||
|
||||
/* zap the old tx dma descriptor address field */
|
||||
W_SM(&di->txd32[old].addr, BUS_SWAP32(0xdeadbeef));
|
||||
|
||||
/* move the corresponding txp[] entry */
|
||||
ASSERT(di->txp[new] == NULL);
|
||||
di->txp[new] = di->txp[old];
|
||||
|
||||
/* Move the segment map as well */
|
||||
if (DMASGLIST_ENAB) {
|
||||
bcopy(&di->txp_dmah[old], &di->txp_dmah[new],
|
||||
sizeof(hnddma_seg_map_t));
|
||||
memset(&di->txp_dmah[old], 0, sizeof(hnddma_seg_map_t));
|
||||
}
|
||||
|
||||
di->txp[old] = NULL;
|
||||
}
|
||||
|
||||
/* update txin and txout */
|
||||
di->txin = ad;
|
||||
di->txout = TXD(di->txout + rot);
|
||||
di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
|
||||
|
||||
/* kick the chip */
|
||||
W_REG(di->osh, &di->d32txregs->ptr, I2B(di->txout, dma32dd_t));
|
||||
}
|
||||
|
||||
/* 64-bit DMA functions */
|
||||
|
||||
static void dma64_txinit(dma_info_t *di)
|
||||
|
|
@ -2455,7 +1789,6 @@ static void dma64_txrotate(dma_info_t *di)
|
|||
|
||||
uint dma_addrwidth(si_t *sih, void *dmaregs)
|
||||
{
|
||||
dma32regs_t *dma32regs;
|
||||
struct osl_info *osh;
|
||||
|
||||
osh = si_osh(sih);
|
||||
|
|
@ -2470,24 +1803,8 @@ uint dma_addrwidth(si_t *sih, void *dmaregs)
|
|||
((sih->bustype == PCI_BUS) &&
|
||||
(sih->buscoretype == PCIE_CORE_ID)))
|
||||
return DMADDRWIDTH_64;
|
||||
|
||||
/* DMA64 is always 32-bit capable, AE is always true */
|
||||
ASSERT(_dma64_addrext(osh, (dma64regs_t *) dmaregs));
|
||||
|
||||
return DMADDRWIDTH_32;
|
||||
}
|
||||
|
||||
/* Start checking for 32-bit / 30-bit addressing */
|
||||
dma32regs = (dma32regs_t *) dmaregs;
|
||||
|
||||
/* For System Backplane, PCIE bus or addrext feature, 32-bits ok */
|
||||
if ((sih->bustype == SI_BUS) ||
|
||||
((sih->bustype == PCI_BUS)
|
||||
&& sih->buscoretype == PCIE_CORE_ID)
|
||||
|| (_dma32_addrext(osh, dma32regs)))
|
||||
return DMADDRWIDTH_32;
|
||||
|
||||
/* Fallthru */
|
||||
return DMADDRWIDTH_30;
|
||||
ASSERT(0); /* DMA hardware not supported by this driver*/
|
||||
return DMADDRWIDTH_64;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue