mirror of
https://github.com/torvalds/linux
synced 2024-09-29 16:00:27 +00:00
Merge branch 'omap-for-v4.13/clkctrl' into omap-for-v4.13/soc-v4
This commit is contained in:
commit
67d00470ac
|
@ -1224,6 +1224,14 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
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return 0;
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}
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u32 clkdm_xlate_address(struct clockdomain *clkdm)
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{
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if (arch_clkdm->clkdm_xlate_address)
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return arch_clkdm->clkdm_xlate_address(clkdm);
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return 0;
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}
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/**
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* clkdm_hwmod_enable - add an enabled downstream hwmod to this clkdm
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* @clkdm: struct clockdomain *
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@ -175,6 +175,7 @@ struct clkdm_ops {
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void (*clkdm_deny_idle)(struct clockdomain *clkdm);
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int (*clkdm_clk_enable)(struct clockdomain *clkdm);
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int (*clkdm_clk_disable)(struct clockdomain *clkdm);
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u32 (*clkdm_xlate_address)(struct clockdomain *clkdm);
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};
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int clkdm_register_platform_funcs(struct clkdm_ops *co);
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@ -213,6 +214,7 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
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int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
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int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh);
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int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
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u32 clkdm_xlate_address(struct clockdomain *clkdm);
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extern void __init omap242x_clockdomains_init(void);
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extern void __init omap243x_clockdomains_init(void);
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@ -24,8 +24,11 @@
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# ifndef __ASSEMBLER__
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#include <linux/clk/ti.h>
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extern void __iomem *cm_base;
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extern void __iomem *cm2_base;
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#include "prcm-common.h"
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extern struct omap_domain_base cm_base;
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extern struct omap_domain_base cm2_base;
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extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2);
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# endif
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@ -52,12 +52,12 @@
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static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
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{
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return readl_relaxed(cm_base + module + idx);
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return readl_relaxed(cm_base.va + module + idx);
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}
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static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
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{
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writel_relaxed(val, cm_base + module + idx);
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writel_relaxed(val, cm_base.va + module + idx);
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}
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/* Read-modify-write a register in a CM module. Caller must lock */
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@ -50,13 +50,13 @@
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/* Read a register in a CM instance */
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static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx)
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{
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return readl_relaxed(cm_base + inst + idx);
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return readl_relaxed(cm_base.va + inst + idx);
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}
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/* Write into a register in a CM */
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static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx)
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{
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writel_relaxed(val, cm_base + inst + idx);
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writel_relaxed(val, cm_base.va + inst + idx);
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}
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/* Read-modify-write a register in CM */
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@ -669,7 +669,8 @@ static struct cm_ll_data omap3xxx_cm_ll_data = {
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int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data)
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{
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omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base + OMAP3430_IVA2_MOD);
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omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base.va +
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OMAP3430_IVA2_MOD);
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return cm_register(&omap3xxx_cm_ll_data);
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}
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@ -32,10 +32,10 @@ static struct cm_ll_data null_cm_ll_data;
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static struct cm_ll_data *cm_ll_data = &null_cm_ll_data;
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/* cm_base: base virtual address of the CM IP block */
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void __iomem *cm_base;
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struct omap_domain_base cm_base;
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/* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */
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void __iomem *cm2_base;
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struct omap_domain_base cm2_base;
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#define CM_NO_CLOCKS 0x1
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#define CM_SINGLE_INSTANCE 0x2
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@ -49,8 +49,8 @@ void __iomem *cm2_base;
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*/
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void __init omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2)
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{
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cm_base = cm;
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cm2_base = cm2;
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cm_base.va = cm;
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cm2_base.va = cm2;
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}
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/**
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@ -315,27 +315,34 @@ int __init omap2_cm_base_init(void)
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struct device_node *np;
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const struct of_device_id *match;
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struct omap_prcm_init_data *data;
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void __iomem *mem;
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struct resource res;
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int ret;
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struct omap_domain_base *mem = NULL;
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for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) {
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data = (struct omap_prcm_init_data *)match->data;
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mem = of_iomap(np, 0);
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if (!mem)
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return -ENOMEM;
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ret = of_address_to_resource(np, 0, &res);
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if (ret)
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return ret;
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if (data->index == TI_CLKM_CM)
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cm_base = mem + data->offset;
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mem = &cm_base;
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if (data->index == TI_CLKM_CM2)
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cm2_base = mem + data->offset;
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mem = &cm2_base;
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data->mem = mem;
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data->mem = ioremap(res.start, resource_size(&res));
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if (mem) {
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mem->pa = res.start + data->offset;
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mem->va = data->mem + data->offset;
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}
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data->np = np;
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if (data->init && (data->flags & CM_SINGLE_INSTANCE ||
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(cm_base && cm2_base)))
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(cm_base.va && cm2_base.va)))
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data->init(data);
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}
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@ -55,7 +55,7 @@
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#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
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#define CLKCTRL_IDLEST_DISABLED 0x3
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static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
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static struct omap_domain_base _cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
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/**
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* omap_cm_base_init - Populates the cm partitions
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@ -65,10 +65,11 @@ static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
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*/
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static void omap_cm_base_init(void)
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{
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_cm_bases[OMAP4430_PRM_PARTITION] = prm_base;
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_cm_bases[OMAP4430_CM1_PARTITION] = cm_base;
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_cm_bases[OMAP4430_CM2_PARTITION] = cm2_base;
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_cm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
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memcpy(&_cm_bases[OMAP4430_PRM_PARTITION], &prm_base, sizeof(prm_base));
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memcpy(&_cm_bases[OMAP4430_CM1_PARTITION], &cm_base, sizeof(cm_base));
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memcpy(&_cm_bases[OMAP4430_CM2_PARTITION], &cm2_base, sizeof(cm2_base));
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memcpy(&_cm_bases[OMAP4430_PRCM_MPU_PARTITION], &prcm_mpu_base,
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sizeof(prcm_mpu_base));
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}
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/* Private functions */
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@ -116,8 +117,8 @@ static u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx)
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{
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BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
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part == OMAP4430_INVALID_PRCM_PARTITION ||
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!_cm_bases[part]);
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return readl_relaxed(_cm_bases[part] + inst + idx);
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!_cm_bases[part].va);
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return readl_relaxed(_cm_bases[part].va + inst + idx);
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}
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/* Write into a register in a CM instance */
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@ -125,8 +126,8 @@ static void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx)
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{
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BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
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part == OMAP4430_INVALID_PRCM_PARTITION ||
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!_cm_bases[part]);
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writel_relaxed(val, _cm_bases[part] + inst + idx);
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!_cm_bases[part].va);
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writel_relaxed(val, _cm_bases[part].va + inst + idx);
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}
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/* Read-modify-write a register in CM1. Caller must lock */
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@ -475,6 +476,14 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
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return 0;
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}
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static u32 omap4_clkdm_xlate_address(struct clockdomain *clkdm)
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{
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u32 addr = _cm_bases[clkdm->prcm_partition].pa + clkdm->cm_inst +
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clkdm->clkdm_offs;
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return addr;
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}
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struct clkdm_ops omap4_clkdm_operations = {
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.clkdm_add_wkdep = omap4_clkdm_add_wkup_sleep_dep,
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.clkdm_del_wkdep = omap4_clkdm_del_wkup_sleep_dep,
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@ -490,6 +499,7 @@ struct clkdm_ops omap4_clkdm_operations = {
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.clkdm_deny_idle = omap4_clkdm_deny_idle,
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.clkdm_clk_enable = omap4_clkdm_clk_enable,
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.clkdm_clk_disable = omap4_clkdm_clk_disable,
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.clkdm_xlate_address = omap4_clkdm_xlate_address,
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};
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struct clkdm_ops am43xx_clkdm_operations = {
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@ -499,6 +509,7 @@ struct clkdm_ops am43xx_clkdm_operations = {
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.clkdm_deny_idle = omap4_clkdm_deny_idle,
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.clkdm_clk_enable = omap4_clkdm_clk_enable,
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.clkdm_clk_disable = omap4_clkdm_clk_disable,
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.clkdm_xlate_address = omap4_clkdm_xlate_address,
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};
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static struct cm_ll_data omap4xxx_cm_ll_data = {
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@ -141,6 +141,7 @@
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#include <linux/cpu.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/bootmem.h>
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#include <asm/system_misc.h>
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@ -181,6 +182,24 @@
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*/
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#define MOD_CLK_MAX_NAME_LEN 32
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/**
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* struct clkctrl_provider - clkctrl provider mapping data
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* @addr: base address for the provider
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* @offset: base offset for the provider
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* @clkdm: base clockdomain for provider
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* @node: device node associated with the provider
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* @link: list link
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*/
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struct clkctrl_provider {
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u32 addr;
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u16 offset;
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struct clockdomain *clkdm;
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struct device_node *node;
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struct list_head link;
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};
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static LIST_HEAD(clkctrl_providers);
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/**
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* struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations
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* @enable_module: function to enable a module (via MODULEMODE)
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|
@ -204,6 +223,8 @@ struct omap_hwmod_soc_ops {
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void (*update_context_lost)(struct omap_hwmod *oh);
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int (*get_context_lost)(struct omap_hwmod *oh);
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int (*disable_direct_prcm)(struct omap_hwmod *oh);
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u32 (*xlate_clkctrl)(struct omap_hwmod *oh,
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struct clkctrl_provider *provider);
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};
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/* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */
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|
@ -690,6 +711,103 @@ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
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return clkdm_del_sleepdep(clkdm, init_clkdm);
|
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}
|
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|
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static const struct of_device_id ti_clkctrl_match_table[] __initconst = {
|
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{ .compatible = "ti,clkctrl" },
|
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{ }
|
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};
|
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|
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static int _match_clkdm(struct clockdomain *clkdm, void *user)
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{
|
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struct clkctrl_provider *provider = user;
|
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|
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if (clkdm_xlate_address(clkdm) == provider->addr) {
|
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pr_debug("%s: Matched clkdm %s for addr %x (%s)\n", __func__,
|
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clkdm->name, provider->addr,
|
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provider->node->parent->name);
|
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provider->clkdm = clkdm;
|
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|
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return -1;
|
||||
}
|
||||
|
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return 0;
|
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}
|
||||
|
||||
static int _setup_clkctrl_provider(struct device_node *np)
|
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{
|
||||
const __be32 *addrp;
|
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struct clkctrl_provider *provider;
|
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|
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provider = memblock_virt_alloc(sizeof(*provider), 0);
|
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if (!provider)
|
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return -ENOMEM;
|
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|
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addrp = of_get_address(np, 0, NULL, NULL);
|
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provider->addr = (u32)of_translate_address(np, addrp);
|
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provider->offset = provider->addr & 0xff;
|
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provider->addr &= ~0xff;
|
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provider->node = np;
|
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|
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clkdm_for_each(_match_clkdm, provider);
|
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|
||||
if (!provider->clkdm) {
|
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pr_err("%s: nothing matched for node %s (%x)\n",
|
||||
__func__, np->parent->name, provider->addr);
|
||||
memblock_free_early(__pa(provider), sizeof(*provider));
|
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return -EINVAL;
|
||||
}
|
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|
||||
list_add(&provider->link, &clkctrl_providers);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _init_clkctrl_providers(void)
|
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{
|
||||
struct device_node *np;
|
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int ret = 0;
|
||||
|
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for_each_matching_node(np, ti_clkctrl_match_table) {
|
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ret = _setup_clkctrl_provider(np);
|
||||
if (ret)
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static u32 _omap4_xlate_clkctrl(struct omap_hwmod *oh,
|
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struct clkctrl_provider *provider)
|
||||
{
|
||||
return oh->prcm.omap4.clkctrl_offs -
|
||||
provider->offset - provider->clkdm->clkdm_offs;
|
||||
}
|
||||
|
||||
static struct clk *_lookup_clkctrl_clk(struct omap_hwmod *oh)
|
||||
{
|
||||
struct clkctrl_provider *provider;
|
||||
struct clk *clk;
|
||||
|
||||
if (!soc_ops.xlate_clkctrl)
|
||||
return NULL;
|
||||
|
||||
list_for_each_entry(provider, &clkctrl_providers, link) {
|
||||
if (provider->clkdm == oh->clkdm) {
|
||||
struct of_phandle_args clkspec;
|
||||
|
||||
clkspec.np = provider->node;
|
||||
clkspec.args_count = 2;
|
||||
clkspec.args[0] = soc_ops.xlate_clkctrl(oh, provider);
|
||||
clkspec.args[1] = 0;
|
||||
|
||||
clk = of_clk_get_from_provider(&clkspec);
|
||||
|
||||
return clk;
|
||||
}
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* _init_main_clk - get a struct clk * for the the hwmod's main functional clk
|
||||
* @oh: struct omap_hwmod *
|
||||
|
@ -701,22 +819,16 @@ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
|
|||
static int _init_main_clk(struct omap_hwmod *oh)
|
||||
{
|
||||
int ret = 0;
|
||||
char name[MOD_CLK_MAX_NAME_LEN];
|
||||
struct clk *clk;
|
||||
static const char modck[] = "_mod_ck";
|
||||
struct clk *clk = NULL;
|
||||
|
||||
if (strlen(oh->name) >= MOD_CLK_MAX_NAME_LEN - strlen(modck))
|
||||
pr_warn("%s: warning: cropping name for %s\n", __func__,
|
||||
oh->name);
|
||||
clk = _lookup_clkctrl_clk(oh);
|
||||
|
||||
strlcpy(name, oh->name, MOD_CLK_MAX_NAME_LEN - strlen(modck));
|
||||
strlcat(name, modck, MOD_CLK_MAX_NAME_LEN);
|
||||
|
||||
clk = clk_get(NULL, name);
|
||||
if (!IS_ERR(clk)) {
|
||||
if (!IS_ERR_OR_NULL(clk)) {
|
||||
pr_debug("%s: mapped main_clk %s for %s\n", __func__,
|
||||
__clk_get_name(clk), oh->name);
|
||||
oh->main_clk = __clk_get_name(clk);
|
||||
oh->_clk = clk;
|
||||
soc_ops.disable_direct_prcm(oh);
|
||||
oh->main_clk = kstrdup(name, GFP_KERNEL);
|
||||
} else {
|
||||
if (!oh->main_clk)
|
||||
return 0;
|
||||
|
@ -1482,13 +1594,13 @@ static int _init_clkdm(struct omap_hwmod *oh)
|
|||
* _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as
|
||||
* well the clockdomain.
|
||||
* @oh: struct omap_hwmod *
|
||||
* @data: not used; pass NULL
|
||||
* @np: device_node mapped to this hwmod
|
||||
*
|
||||
* Called by omap_hwmod_setup_*() (after omap2_clk_init()).
|
||||
* Resolves all clock names embedded in the hwmod. Returns 0 on
|
||||
* success, or a negative error code on failure.
|
||||
*/
|
||||
static int _init_clocks(struct omap_hwmod *oh, void *data)
|
||||
static int _init_clocks(struct omap_hwmod *oh, struct device_node *np)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
|
@ -2357,7 +2469,7 @@ static int __init _init(struct omap_hwmod *oh, void *data)
|
|||
return 0;
|
||||
}
|
||||
|
||||
r = _init_clocks(oh, NULL);
|
||||
r = _init_clocks(oh, np);
|
||||
if (r < 0) {
|
||||
WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name);
|
||||
return -EINVAL;
|
||||
|
@ -3719,6 +3831,7 @@ void __init omap_hwmod_init(void)
|
|||
soc_ops.update_context_lost = _omap4_update_context_lost;
|
||||
soc_ops.get_context_lost = _omap4_get_context_lost;
|
||||
soc_ops.disable_direct_prcm = _omap4_disable_direct_prcm;
|
||||
soc_ops.xlate_clkctrl = _omap4_xlate_clkctrl;
|
||||
} else if (cpu_is_ti814x() || cpu_is_ti816x() || soc_is_am33xx() ||
|
||||
soc_is_am43xx()) {
|
||||
soc_ops.enable_module = _omap4_enable_module;
|
||||
|
@ -3733,6 +3846,8 @@ void __init omap_hwmod_init(void)
|
|||
WARN(1, "omap_hwmod: unknown SoC type\n");
|
||||
}
|
||||
|
||||
_init_clkctrl_providers();
|
||||
|
||||
inited = true;
|
||||
}
|
||||
|
||||
|
|
|
@ -775,6 +775,7 @@ static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
|
|||
|
||||
static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
|
||||
{ .role = "sys_clk", .clk = "dss_sys_clk" },
|
||||
{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
|
||||
|
@ -785,7 +786,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
|
|||
* HDMI audio requires to use no-idle mode. Hence,
|
||||
* set idle mode by software.
|
||||
*/
|
||||
.flags = HWMOD_SWSUP_SIDLE,
|
||||
.flags = HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
|
||||
.mpu_irqs = omap44xx_dss_hdmi_irqs,
|
||||
.xlate_irq = omap4_xlate_irq,
|
||||
.sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
|
||||
|
@ -858,11 +859,16 @@ static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
|
|||
};
|
||||
|
||||
/* dss_venc */
|
||||
static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
|
||||
{ .role = "tv_clk", .clk = "dss_tv_clk" },
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_dss_venc_hwmod = {
|
||||
.name = "dss_venc",
|
||||
.class = &omap44xx_venc_hwmod_class,
|
||||
.clkdm_name = "l3_dss_clkdm",
|
||||
.main_clk = "dss_tv_clk",
|
||||
.flags = HWMOD_OPT_CLKS_NEEDED,
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
|
||||
|
@ -870,6 +876,8 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
|
|||
},
|
||||
},
|
||||
.parent_hwmod = &omap44xx_dss_hwmod,
|
||||
.opt_clks = dss_venc_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
|
@ -526,10 +526,16 @@ struct omap_prcm_irq_setup {
|
|||
.priority = _priority \
|
||||
}
|
||||
|
||||
struct omap_domain_base {
|
||||
u32 pa;
|
||||
void __iomem *va;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct omap_prcm_init_data - PRCM driver init data
|
||||
* @index: clock memory mapping index to be used
|
||||
* @mem: IO mem pointer for this module
|
||||
* @phys: IO mem physical base address for this module
|
||||
* @offset: module base address offset from the IO base
|
||||
* @flags: PRCM module init flags
|
||||
* @device_inst_offset: device instance offset within the module address space
|
||||
|
@ -539,6 +545,7 @@ struct omap_prcm_irq_setup {
|
|||
struct omap_prcm_init_data {
|
||||
int index;
|
||||
void __iomem *mem;
|
||||
u32 phys;
|
||||
s16 offset;
|
||||
u16 flags;
|
||||
s32 device_inst_offset;
|
||||
|
|
|
@ -24,7 +24,7 @@
|
|||
* prcm_mpu_base: the virtual address of the start of the PRCM_MPU IP
|
||||
* block registers
|
||||
*/
|
||||
void __iomem *prcm_mpu_base;
|
||||
struct omap_domain_base prcm_mpu_base;
|
||||
|
||||
/* PRCM_MPU low-level functions */
|
||||
|
||||
|
@ -58,5 +58,5 @@ u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
|
|||
*/
|
||||
void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu)
|
||||
{
|
||||
prcm_mpu_base = prcm_mpu;
|
||||
prcm_mpu_base.va = prcm_mpu;
|
||||
}
|
||||
|
|
|
@ -24,7 +24,9 @@
|
|||
#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
extern void __iomem *prcm_mpu_base;
|
||||
#include "prcm-common.h"
|
||||
|
||||
extern struct omap_domain_base prcm_mpu_base;
|
||||
|
||||
extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
|
||||
extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
|
||||
|
|
|
@ -16,7 +16,7 @@
|
|||
#include "prcm-common.h"
|
||||
|
||||
# ifndef __ASSEMBLER__
|
||||
extern void __iomem *prm_base;
|
||||
extern struct omap_domain_base prm_base;
|
||||
extern u16 prm_features;
|
||||
extern void omap2_set_globals_prm(void __iomem *prm);
|
||||
int omap_prcm_init(void);
|
||||
|
|
|
@ -55,12 +55,12 @@
|
|||
/* Power/reset management domain register get/set */
|
||||
static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
|
||||
{
|
||||
return readl_relaxed(prm_base + module + idx);
|
||||
return readl_relaxed(prm_base.va + module + idx);
|
||||
}
|
||||
|
||||
static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
|
||||
{
|
||||
writel_relaxed(val, prm_base + module + idx);
|
||||
writel_relaxed(val, prm_base.va + module + idx);
|
||||
}
|
||||
|
||||
/* Read-modify-write a register in a PRM module. Caller must lock */
|
||||
|
|
|
@ -30,13 +30,13 @@
|
|||
/* Read a register in a PRM instance */
|
||||
static u32 am33xx_prm_read_reg(s16 inst, u16 idx)
|
||||
{
|
||||
return readl_relaxed(prm_base + inst + idx);
|
||||
return readl_relaxed(prm_base.va + inst + idx);
|
||||
}
|
||||
|
||||
/* Write into a register in a PRM instance */
|
||||
static void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
|
||||
{
|
||||
writel_relaxed(val, prm_base + inst + idx);
|
||||
writel_relaxed(val, prm_base.va + inst + idx);
|
||||
}
|
||||
|
||||
/* Read-modify-write a register in PRM. Caller must lock */
|
||||
|
|
|
@ -676,7 +676,7 @@ static struct prm_ll_data omap3xxx_prm_ll_data = {
|
|||
int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data)
|
||||
{
|
||||
omap2_clk_legacy_provider_init(TI_CLKM_PRM,
|
||||
prm_base + OMAP3430_IVA2_MOD);
|
||||
prm_base.va + OMAP3430_IVA2_MOD);
|
||||
if (omap3_has_io_wakeup())
|
||||
prm_features |= PRM_HAS_IO_WAKEUP;
|
||||
|
||||
|
|
|
@ -91,13 +91,13 @@ static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
|
|||
/* Read a register in a CM/PRM instance in the PRM module */
|
||||
static u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
|
||||
{
|
||||
return readl_relaxed(prm_base + inst + reg);
|
||||
return readl_relaxed(prm_base.va + inst + reg);
|
||||
}
|
||||
|
||||
/* Write into a register in a CM/PRM instance in the PRM module */
|
||||
static void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
|
||||
{
|
||||
writel_relaxed(val, prm_base + inst + reg);
|
||||
writel_relaxed(val, prm_base.va + inst + reg);
|
||||
}
|
||||
|
||||
/* Read-modify-write a register in a PRM module. Caller must lock */
|
||||
|
|
|
@ -66,7 +66,7 @@ static struct irq_chip_generic **prcm_irq_chips;
|
|||
static struct omap_prcm_irq_setup *prcm_irq_setup;
|
||||
|
||||
/* prm_base: base virtual address of the PRM IP block */
|
||||
void __iomem *prm_base;
|
||||
struct omap_domain_base prm_base;
|
||||
|
||||
u16 prm_features;
|
||||
|
||||
|
@ -324,7 +324,7 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
|
|||
|
||||
for (i = 0; i < irq_setup->nr_regs; i++) {
|
||||
gc = irq_alloc_generic_chip("PRCM", 1,
|
||||
irq_setup->base_irq + i * 32, prm_base,
|
||||
irq_setup->base_irq + i * 32, prm_base.va,
|
||||
handle_level_irq);
|
||||
|
||||
if (!gc) {
|
||||
|
@ -361,7 +361,7 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
|
|||
*/
|
||||
void __init omap2_set_globals_prm(void __iomem *prm)
|
||||
{
|
||||
prm_base = prm;
|
||||
prm_base.va = prm;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -752,19 +752,22 @@ int __init omap2_prm_base_init(void)
|
|||
struct device_node *np;
|
||||
const struct of_device_id *match;
|
||||
struct omap_prcm_init_data *data;
|
||||
void __iomem *mem;
|
||||
struct resource res;
|
||||
int ret;
|
||||
|
||||
for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) {
|
||||
data = (struct omap_prcm_init_data *)match->data;
|
||||
|
||||
mem = of_iomap(np, 0);
|
||||
if (!mem)
|
||||
return -ENOMEM;
|
||||
ret = of_address_to_resource(np, 0, &res);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (data->index == TI_CLKM_PRM)
|
||||
prm_base = mem + data->offset;
|
||||
data->mem = ioremap(res.start, resource_size(&res));
|
||||
|
||||
data->mem = mem;
|
||||
if (data->index == TI_CLKM_PRM) {
|
||||
prm_base.va = data->mem + data->offset;
|
||||
prm_base.pa = res.start + data->offset;
|
||||
}
|
||||
|
||||
data->np = np;
|
||||
|
||||
|
|
|
@ -29,7 +29,7 @@
|
|||
#include "prcm_mpu44xx.h"
|
||||
#include "soc.h"
|
||||
|
||||
static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
|
||||
static struct omap_domain_base _prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
|
||||
|
||||
static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN;
|
||||
|
||||
|
@ -41,8 +41,10 @@ static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN;
|
|||
*/
|
||||
void omap_prm_base_init(void)
|
||||
{
|
||||
_prm_bases[OMAP4430_PRM_PARTITION] = prm_base;
|
||||
_prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
|
||||
memcpy(&_prm_bases[OMAP4430_PRM_PARTITION], &prm_base,
|
||||
sizeof(prm_base));
|
||||
memcpy(&_prm_bases[OMAP4430_PRCM_MPU_PARTITION], &prcm_mpu_base,
|
||||
sizeof(prcm_mpu_base));
|
||||
}
|
||||
|
||||
s32 omap4_prmst_get_prm_dev_inst(void)
|
||||
|
@ -60,8 +62,8 @@ u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
|
|||
{
|
||||
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
|
||||
part == OMAP4430_INVALID_PRCM_PARTITION ||
|
||||
!_prm_bases[part]);
|
||||
return readl_relaxed(_prm_bases[part] + inst + idx);
|
||||
!_prm_bases[part].va);
|
||||
return readl_relaxed(_prm_bases[part].va + inst + idx);
|
||||
}
|
||||
|
||||
/* Write into a register in a PRM instance */
|
||||
|
@ -69,8 +71,8 @@ void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
|
|||
{
|
||||
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
|
||||
part == OMAP4430_INVALID_PRCM_PARTITION ||
|
||||
!_prm_bases[part]);
|
||||
writel_relaxed(val, _prm_bases[part] + inst + idx);
|
||||
!_prm_bases[part].va);
|
||||
writel_relaxed(val, _prm_bases[part].va + inst + idx);
|
||||
}
|
||||
|
||||
/* Read-modify-write a register in PRM. Caller must lock */
|
||||
|
|
|
@ -272,6 +272,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
|
|||
|
||||
timer->io_base = of_iomap(np, 0);
|
||||
|
||||
timer->fclk = of_clk_get_by_name(np, "fck");
|
||||
|
||||
of_node_put(np);
|
||||
|
||||
oh = omap_hwmod_lookup(oh_name);
|
||||
|
@ -286,7 +288,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
|
|||
omap_hwmod_setup_one(oh_name);
|
||||
|
||||
/* After the dmtimer is using hwmod these clocks won't be needed */
|
||||
timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
|
||||
if (IS_ERR_OR_NULL(timer->fclk))
|
||||
timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
|
||||
if (IS_ERR(timer->fclk))
|
||||
return PTR_ERR(timer->fclk);
|
||||
|
||||
|
|
Loading…
Reference in a new issue