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IOMMU Fixes for Linux v4.10-rc2

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Three fixes queued up:
 
 	* Fix an issue with command buffer overflow handling in the AMD
 	  IOMMU driver
 
 	* Add an additional context entry flush to the Intel VT-d driver
 	  to make sure any old context entry from kdump copying is
 	  flushed out of the cache
 
 	* Correct the encoding of the PASID table size in the Intel VT-d
 	  driver
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABAgAGBQJYb6+0AAoJECvwRC2XARrjDh4QAN6frtp8eu+klRWL2/l3JdZA
 Iht+HfwC6RCq7Rl8fqqjcfyFXImb+QazfKnyFriH/RxohV9PD5LqLVSmlngoficb
 vuas7ZQB1+fUUz4pPkJOEium5QhVn+RFHgnJPke685EsASVb9/QJBswzrhAvAM0X
 RYli/hZ2+MpWeQdmF8pWgO0Dt5ker4bT+9AnYyz8IUJgyQeqZPucoPwksnjvouJz
 och0IWvfNH3OGRIM5MDpJ5h9W7fdxVL5tS0KJ+NyXLBSqEr7fmKtJgwwxSIOJUIN
 7J+1ASu/fHvegCVG9eNELEy9RPKCp/Ju6mgw4AtVDHDG5IRKKX9T/ab+6d3PIPE5
 jZxycerGip5NV4TieK9abk9mw4I+NOyKn4OdyC6ZrGwF73rdqNG7mljLlFE39HR8
 Qvua1bMhykcpKwSJpb52InbYEFkb09Rn6/AVDSpby9WnDai2wdcn+YFtgZrnYevD
 e3HoO+X1VrmSRlTxG6yPvPmcYhCZxl7W+duzPYd9Ff4aS4VA24xgfMs5w1dsu3Tt
 hb/BqMmQ4bSUQqaemj2JpJqVBRlXQc5pkFFtQtdrAO6xWyrQXcjZemzHRBMAmtZP
 xI8ksD5L9QRbg/KTKcYNFSQ6WVZMBV2dTXWhEycLkGokGDXGCis0BF6IRXTwJNQU
 9cLOXtL9hyBBm7tKn199
 =wit6
 -----END PGP SIGNATURE-----

Merge tag 'iommu-fixes-v4.10-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu

Pull IOMMU fixes from Joerg Roedel:
 "Three fixes queued up:

   - fix an issue with command buffer overflow handling in the AMD IOMMU
     driver

   - add an additional context entry flush to the Intel VT-d driver to
     make sure any old context entry from kdump copying is flushed out
     of the cache

   - correct the encoding of the PASID table size in the Intel VT-d
     driver"

* tag 'iommu-fixes-v4.10-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
  iommu/amd: Fix the left value check of cmd buffer
  iommu/vt-d: Fix pasid table size encoding
  iommu/vt-d: Flush old iommu caches for kdump when the device gets context mapped
This commit is contained in:
Linus Torvalds 2017-01-06 10:49:36 -08:00
parent 7397e1e838 432abf68a7
commit 65cdc405b3
2 changed files with 42 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
drivers/iommu/amd_iommu.c
View file

@ -1023,7 +1023,7 @@ static int __iommu_queue_command_sync(struct amd_iommu *iommu,
next_tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
left = (head - next_tail) % CMD_BUFFER_SIZE;
if (left <= 2) {
if (left <= 0x20) {
struct iommu_cmd sync_cmd;
int ret;

42
drivers/iommu/intel-iommu.c
View file

@ -2037,6 +2037,25 @@ static int domain_context_mapping_one(struct dmar_domain *domain,
if (context_present(context))
goto out_unlock;
/*
* For kdump cases, old valid entries may be cached due to the
* in-flight DMA and copied pgtable, but there is no unmapping
* behaviour for them, thus we need an explicit cache flush for
* the newly-mapped device. For kdump, at this point, the device
* is supposed to finish reset at its driver probe stage, so no
* in-flight DMA will exist, and we don't need to worry anymore
* hereafter.
*/
if (context_copied(context)) {
u16 did_old = context_domain_id(context);
if (did_old >= 0 && did_old < cap_ndoms(iommu->cap))
iommu->flush.flush_context(iommu, did_old,
(((u16)bus) << 8) | devfn,
DMA_CCMD_MASK_NOBIT,
DMA_CCMD_DEVICE_INVL);
}
pgd = domain->pgd;
context_clear_entry(context);
@ -5185,6 +5204,25 @@ static void intel_iommu_remove_device(struct device *dev)
}
#ifdef CONFIG_INTEL_IOMMU_SVM
#define MAX_NR_PASID_BITS (20)
static inline unsigned long intel_iommu_get_pts(struct intel_iommu *iommu)
{
/*
* Convert ecap_pss to extend context entry pts encoding, also
* respect the soft pasid_max value set by the iommu.
* - number of PASID bits = ecap_pss + 1
* - number of PASID table entries = 2^(pts + 5)
* Therefore, pts = ecap_pss - 4
* e.g. KBL ecap_pss = 0x13, PASID has 20 bits, pts = 15
*/
if (ecap_pss(iommu->ecap) < 5)
return 0;
/* pasid_max is encoded as actual number of entries not the bits */
return find_first_bit((unsigned long *)&iommu->pasid_max,
MAX_NR_PASID_BITS) - 5;
}
int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sdev)
{
struct device_domain_info *info;
@ -5217,7 +5255,9 @@ int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sd
if (!(ctx_lo & CONTEXT_PASIDE)) {
context[1].hi = (u64)virt_to_phys(iommu->pasid_state_table);
context[1].lo = (u64)virt_to_phys(iommu->pasid_table) | ecap_pss(iommu->ecap);
context[1].lo = (u64)virt_to_phys(iommu->pasid_table) |
intel_iommu_get_pts(iommu);
wmb();
/* CONTEXT_TT_MULTI_LEVEL and CONTEXT_TT_DEV_IOTLB are both
* extended to permit requests-with-PASID if the PASIDE bit