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ARM: zynq: Use restart_handler mechanism for slcr reset

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By making use of the restart_handler chain mechanism, the SLCR-based
reset mechanism can be prioritized amongst other mechanisms available on
a particular board.

Choose a default high-ish priority of 192 for this restart mechanism.

Signed-off-by: Josh Cartwright <joshc@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Josh Cartwright 2015-03-19 09:24:38 -05:00 committed by Michal Simek
parent b787f68c36
commit 64e6861760
3 changed files with 19 additions and 9 deletions
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6
arch/arm/mach-zynq/common.c
View file

@ -190,11 +190,6 @@ static void __init zynq_irq_init(void)
irqchip_init();
}
static void zynq_system_reset(enum reboot_mode mode, const char *cmd)
{
zynq_slcr_system_reset();
}
static const char * const zynq_dt_match[] = {
"xlnx,zynq-7000",
NULL
@ -212,5 +207,4 @@ DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
.init_time = zynq_timer_init,
.dt_compat = zynq_dt_match,
.reserve = zynq_memory_init,
.restart = zynq_system_reset,
MACHINE_END

1
arch/arm/mach-zynq/common.h
View file

@ -21,7 +21,6 @@ void zynq_secondary_startup(void);
extern int zynq_slcr_init(void);
extern int zynq_early_slcr_init(void);
extern void zynq_slcr_system_reset(void);
extern void zynq_slcr_cpu_stop(int cpu);
extern void zynq_slcr_cpu_start(int cpu);
extern bool zynq_slcr_cpu_state_read(int cpu);

21
arch/arm/mach-zynq/slcr.c
View file

@ -15,6 +15,7 @@
*/
#include <linux/io.h>
#include <linux/reboot.h>
#include <linux/mfd/syscon.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
@ -92,9 +93,17 @@ u32 zynq_slcr_get_device_id(void)
}
/**
* zynq_slcr_system_reset - Reset the entire system.
* zynq_slcr_system_restart - Restart the entire system.
*
* @nb: Pointer to restart notifier block (unused)
* @action: Reboot mode (unused)
* @data: Restart handler private data (unused)
*
* Return: 0 always
*/
void zynq_slcr_system_reset(void)
static
int zynq_slcr_system_restart(struct notifier_block *nb,
unsigned long action, void *data)
{
u32 reboot;
@ -113,8 +122,14 @@ void zynq_slcr_system_reset(void)
zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET);
zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET);
zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET);
return 0;
}
static struct notifier_block zynq_slcr_restart_nb = {
.notifier_call = zynq_slcr_system_restart,
.priority = 192,
};
/**
* zynq_slcr_cpu_start - Start cpu
* @cpu: cpu number
@ -219,6 +234,8 @@ int __init zynq_early_slcr_init(void)
/* unlock the SLCR so that registers can be changed */
zynq_slcr_unlock();
register_restart_handler(&zynq_slcr_restart_nb);
pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
of_node_put(np);