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ath5k: disable 32KHz sleep clock operation by default
While 32 KHz sleep clock might provide some power saving benefits, it is also a major source of stability issues, on OpenWrt it produced some reproducible data bus errors on register accesses on several different MIPS platforms. All the Atheros drivers that I can find do not enable this feature, so it makes sense to leave it disabled in ath5k as well. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Acked-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -1067,6 +1067,8 @@ struct ath5k_hw {
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u8 ah_retry_long;
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u8 ah_retry_short;
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u32 ah_use_32khz_clock;
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u8 ah_coverage_class;
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bool ah_ack_bitrate_high;
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u8 ah_bwmode;
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@ -922,6 +922,9 @@ ath5k_debug_init_device(struct ath5k_softc *sc)
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debugfs_create_file("queue", S_IWUSR | S_IRUSR, phydir, sc,
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&fops_queue);
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debugfs_create_bool("32khz_clock", S_IWUSR | S_IRUSR, phydir,
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&sc->ah->ah_use_32khz_clock);
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}
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/* functions used in other places */
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@ -1287,11 +1287,16 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
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ath5k_hw_dma_init(ah);
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/* Enable 32KHz clock function for AR5212+ chips
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/*
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* Enable 32KHz clock function for AR5212+ chips
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* Set clocks to 32KHz operation and use an
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* external 32KHz crystal when sleeping if one
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* exists */
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if (ah->ah_version == AR5K_AR5212 &&
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* exists.
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* Disabled by default because it is also disabled in
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* other drivers and it is known to cause stability
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* issues on some devices
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*/
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if (ah->ah_use_32khz_clock && ah->ah_version == AR5K_AR5212 &&
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op_mode != NL80211_IFTYPE_AP)
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ath5k_hw_set_sleep_clock(ah, true);
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