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drm/radeon/kms: demystify evergreen blit code
some bits in 3D registers used by blit functions look like magic and this is hard to follow; change them to a little bit more meaningful pre-defined constants Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Ilija Hadzic
Dave Airlie
parent
7dbf41db32
commit
6018faf58d
2 changed files with 62 additions and 9 deletions
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@ -60,7 +60,9 @@ set_render_target(struct radeon_device *rdev, int format,
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if (h < 8)
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h = 8;
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cb_color_info = ((format << 2) | (1 << 24) | (2 << 8));
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cb_color_info = CB_FORMAT(format) |
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CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) |
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CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
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pitch = (w / 8) - 1;
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slice = ((w * h) / 64) - 1;
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@ -137,12 +139,16 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
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u32 sq_vtx_constant_word2, sq_vtx_constant_word3;
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/* high addr, stride */
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sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8));
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sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
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SQ_VTXC_STRIDE(16);
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#ifdef __BIG_ENDIAN
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sq_vtx_constant_word2 |= (2 << 30);
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sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
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#endif
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/* xyzw swizzles */
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sq_vtx_constant_word3 = (0 << 3) | (1 << 6) | (2 << 9) | (3 << 12);
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sq_vtx_constant_word3 = SQ_VTCX_SEL_X(SQ_SEL_X) |
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SQ_VTCX_SEL_Y(SQ_SEL_Y) |
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SQ_VTCX_SEL_Z(SQ_SEL_Z) |
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SQ_VTCX_SEL_W(SQ_SEL_W);
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8));
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radeon_ring_write(rdev, 0x580);
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@ -153,7 +159,7 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
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radeon_ring_write(rdev, 0);
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radeon_ring_write(rdev, 0);
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radeon_ring_write(rdev, 0);
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radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
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radeon_ring_write(rdev, S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_BUFFER));
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if ((rdev->family == CHIP_CEDAR) ||
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(rdev->family == CHIP_PALM) ||
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@ -180,14 +186,19 @@ set_tex_resource(struct radeon_device *rdev,
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if (h < 1)
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h = 1;
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sq_tex_resource_word0 = (1 << 0); /* 2D */
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sq_tex_resource_word0 = TEX_DIM(SQ_TEX_DIM_2D);
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sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 6) |
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((w - 1) << 18));
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sq_tex_resource_word1 = ((h - 1) << 0) | (2 << 28);
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sq_tex_resource_word1 = ((h - 1) << 0) |
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TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
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/* xyzw swizzles */
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sq_tex_resource_word4 = (0 << 16) | (1 << 19) | (2 << 22) | (3 << 25);
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sq_tex_resource_word4 = TEX_DST_SEL_X(SQ_SEL_X) |
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TEX_DST_SEL_Y(SQ_SEL_Y) |
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TEX_DST_SEL_Z(SQ_SEL_Z) |
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TEX_DST_SEL_W(SQ_SEL_W);
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sq_tex_resource_word7 = format | (SQ_TEX_VTX_VALID_TEXTURE << 30);
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sq_tex_resource_word7 = format |
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S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_TEXTURE);
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8));
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radeon_ring_write(rdev, 0);
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@ -941,11 +941,15 @@
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#define CB_COLOR0_SLICE 0x28c68
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#define CB_COLOR0_VIEW 0x28c6c
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#define CB_COLOR0_INFO 0x28c70
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# define CB_FORMAT(x) ((x) << 2)
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# define CB_ARRAY_MODE(x) ((x) << 8)
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# define ARRAY_LINEAR_GENERAL 0
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# define ARRAY_LINEAR_ALIGNED 1
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# define ARRAY_1D_TILED_THIN1 2
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# define ARRAY_2D_TILED_THIN1 4
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# define CB_SOURCE_FORMAT(x) ((x) << 24)
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# define CB_SF_EXPORT_FULL 0
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# define CB_SF_EXPORT_NORM 1
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#define CB_COLOR0_ATTRIB 0x28c74
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#define CB_COLOR0_DIM 0x28c78
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/* only CB0-7 blocks have these regs */
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@ -1107,15 +1111,53 @@
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#define CB_COLOR7_CLEAR_WORD3 0x28e3c
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#define SQ_TEX_RESOURCE_WORD0_0 0x30000
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# define TEX_DIM(x) ((x) << 0)
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# define SQ_TEX_DIM_1D 0
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# define SQ_TEX_DIM_2D 1
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# define SQ_TEX_DIM_3D 2
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# define SQ_TEX_DIM_CUBEMAP 3
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# define SQ_TEX_DIM_1D_ARRAY 4
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# define SQ_TEX_DIM_2D_ARRAY 5
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# define SQ_TEX_DIM_2D_MSAA 6
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# define SQ_TEX_DIM_2D_ARRAY_MSAA 7
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#define SQ_TEX_RESOURCE_WORD1_0 0x30004
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# define TEX_ARRAY_MODE(x) ((x) << 28)
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#define SQ_TEX_RESOURCE_WORD2_0 0x30008
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#define SQ_TEX_RESOURCE_WORD3_0 0x3000C
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#define SQ_TEX_RESOURCE_WORD4_0 0x30010
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# define TEX_DST_SEL_X(x) ((x) << 16)
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# define TEX_DST_SEL_Y(x) ((x) << 19)
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# define TEX_DST_SEL_Z(x) ((x) << 22)
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# define TEX_DST_SEL_W(x) ((x) << 25)
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# define SQ_SEL_X 0
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# define SQ_SEL_Y 1
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# define SQ_SEL_Z 2
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# define SQ_SEL_W 3
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# define SQ_SEL_0 4
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# define SQ_SEL_1 5
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#define SQ_TEX_RESOURCE_WORD5_0 0x30014
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#define SQ_TEX_RESOURCE_WORD6_0 0x30018
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#define SQ_TEX_RESOURCE_WORD7_0 0x3001c
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#define SQ_VTX_CONSTANT_WORD0_0 0x30000
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#define SQ_VTX_CONSTANT_WORD1_0 0x30004
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#define SQ_VTX_CONSTANT_WORD2_0 0x30008
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# define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0)
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# define SQ_VTXC_STRIDE(x) ((x) << 8)
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# define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30)
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# define SQ_ENDIAN_NONE 0
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# define SQ_ENDIAN_8IN16 1
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# define SQ_ENDIAN_8IN32 2
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#define SQ_VTX_CONSTANT_WORD3_0 0x3000C
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# define SQ_VTCX_SEL_X(x) ((x) << 3)
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# define SQ_VTCX_SEL_Y(x) ((x) << 6)
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# define SQ_VTCX_SEL_Z(x) ((x) << 9)
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# define SQ_VTCX_SEL_W(x) ((x) << 12)
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#define SQ_VTX_CONSTANT_WORD4_0 0x30010
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#define SQ_VTX_CONSTANT_WORD5_0 0x30014
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#define SQ_VTX_CONSTANT_WORD6_0 0x30018
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#define SQ_VTX_CONSTANT_WORD7_0 0x3001c
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/* cayman 3D regs */
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#define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B0
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#define CAYMAN_DB_EQAA 0x28804
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