system/linux
system/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux synced 2024-09-21 19:47:35 +00:00
Code Issues Packages Projects Releases Wiki Activity

clk: exynos5440: move restart code into clock driver

Browse source 
Let's register restart handler for Exynos5440 from it's clock driver
for restart functionality. So that we can cleanup restart hooks from
machine specific file.

CC: Sylwester Nawrocki <s.nawrocki@samsung.com>
CC: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Pankaj Dubey 2014-11-22 23:07:21 +09:00 committed by Kukjin Kim
parent 8fcc774fc7
commit 5e6473f422
2 changed files with 29 additions and 19 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

19
arch/arm/mach-exynos/exynos.c
View file

@ -139,24 +139,7 @@ static struct map_desc exynos5_iodesc[] __initdata = {
static void exynos_restart(enum reboot_mode mode, const char *cmd)
{
struct device_node *np;
u32 val = 0x1;
void __iomem *addr = pmu_base_addr + EXYNOS_SWRESET;
if (of_machine_is_compatible("samsung,exynos5440")) {
u32 status;
np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
addr = of_iomap(np, 0) + 0xbc;
status = __raw_readl(addr);
addr = of_iomap(np, 0) + 0xcc;
val = __raw_readl(addr);
val = (val & 0xffff0000) | (status & 0xffff);
}
__raw_writel(val, addr);
__raw_writel(0x1, pmu_base_addr + EXYNOS_SWRESET);
}
static struct platform_device exynos_cpuidle = {

29
drivers/clk/samsung/clk-exynos5440.c
View file

@ -15,6 +15,8 @@
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/notifier.h>
#include <linux/reboot.h>
#include "clk.h"
#include "clk-pll.h"
@ -23,6 +25,8 @@
#define CPU_CLK_STATUS 0xfc
#define MISC_DOUT1 0x558
static void __iomem *reg_base;
/* parent clock name list */
PNAME(mout_armclk_p) = { "cplla", "cpllb" };
PNAME(mout_spi_p) = { "div125", "div200" };
@ -89,10 +93,30 @@ static const struct of_device_id ext_clk_match[] __initconst = {
{},
};
static int exynos5440_clk_restart_notify(struct notifier_block *this,
unsigned long code, void *unused)
{
u32 val, status;
status = readl_relaxed(reg_base + 0xbc);
val = readl_relaxed(reg_base + 0xcc);
val = (val & 0xffff0000) | (status & 0xffff);
writel_relaxed(val, reg_base + 0xcc);
return NOTIFY_DONE;
}
/*
* Exynos5440 Clock restart notifier, handles restart functionality
*/
static struct notifier_block exynos5440_clk_restart_handler = {
.notifier_call = exynos5440_clk_restart_notify,
.priority = 128,
};
/* register exynos5440 clocks */
static void __init exynos5440_clk_init(struct device_node *np)
{
void __iomem *reg_base;
struct samsung_clk_provider *ctx;
reg_base = of_iomap(np, 0);
@ -125,6 +149,9 @@ static void __init exynos5440_clk_init(struct device_node *np)
samsung_clk_of_add_provider(np, ctx);
if (register_restart_handler(&exynos5440_clk_restart_handler))
pr_warn("exynos5440 clock can't register restart handler\n");
pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk"));
pr_info("exynos5440 clock initialization complete\n");
}