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https://github.com/torvalds/linux
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A few MIPS fixes for 5.0:
- Fix IPI handling for Lantiq SoCs, which was broken by changes made back in v4.12. - Enable OF/DT serial support in ath79_defconfig to give us working serial by default. - Fix 64b builds for the Jazz platform. - Set up a struct device for the BCM47xx SoC to allow BCM47xx drivers to perform DMA again following the major DMA mapping changes made in v4.19. - Disable MSI on Cavium Octeon systems when the pcie_disable command line parameter introduced in v3.3 is used, in order to avoid inadvetently accessing PCIe controller registers despite the command line. - Fix a build failure for Cavium Octeon kernels with kexec enabled, introduced in v4.20. - Fix a regression in the behaviour of semctl/shmctl/msgctl IPC syscalls for kernels including n32 support but not o32 support caused by some cleanup in v3.19. -----BEGIN PGP SIGNATURE----- iIsEABYIADMWIQRgLjeFAZEXQzy86/s+p5+stXUA3QUCXEJhqRUccGF1bC5idXJ0 b25AbWlwcy5jb20ACgkQPqefrLV1AN2aWwEA4ZExeZQi+g9oPNII/jd9wbLKU4Eq xjl/+NdzPVu+pP4A/AuG5hsEMFIgS2U0k2js7kNMHCzoV9Ky2m3kdbSNHvQI =AqoC -----END PGP SIGNATURE----- Merge tag 'mips_fixes_5.0_2' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS fixes from Paul Burton: - Fix IPI handling for Lantiq SoCs, which was broken by changes made back in v4.12. - Enable OF/DT serial support in ath79_defconfig to give us working serial by default. - Fix 64b builds for the Jazz platform. - Set up a struct device for the BCM47xx SoC to allow BCM47xx drivers to perform DMA again following the major DMA mapping changes made in v4.19. - Disable MSI on Cavium Octeon systems when the pcie_disable command line parameter introduced in v3.3 is used, in order to avoid inadvetently accessing PCIe controller registers despite the command line. - Fix a build failure for Cavium Octeon kernels with kexec enabled, introduced in v4.20. - Fix a regression in the behaviour of semctl/shmctl/msgctl IPC syscalls for kernels including n32 support but not o32 support caused by some cleanup in v3.19. * tag 'mips_fixes_5.0_2' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: MIPS: OCTEON: fix kexec support mips: fix n32 compat_ipc_parse_version Disable MSI also when pcie-octeon.pcie_disable on MIPS: BCM47XX: Setup struct device for the SoC MIPS: jazz: fix 64bit build MIPS: ath79: Enable OF serial ports in the default config MIPS: lantiq: Use CP0_LEGACY_COMPARE_IRQ MIPS: lantiq: Fix IPI interrupt handling
This commit is contained in:
commit
5d5c303ea0
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@ -3155,6 +3155,7 @@ config MIPS32_O32
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config MIPS32_N32
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bool "Kernel support for n32 binaries"
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depends on 64BIT
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select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
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select COMPAT
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select MIPS32_COMPAT
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select SYSVIPC_COMPAT if SYSVIPC
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@ -173,6 +173,31 @@ void __init plat_mem_setup(void)
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pm_power_off = bcm47xx_machine_halt;
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}
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#ifdef CONFIG_BCM47XX_BCMA
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static struct device * __init bcm47xx_setup_device(void)
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{
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struct device *dev;
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int err;
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dev = kzalloc(sizeof(*dev), GFP_KERNEL);
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if (!dev)
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return NULL;
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err = dev_set_name(dev, "bcm47xx_soc");
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if (err) {
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pr_err("Failed to set SoC device name: %d\n", err);
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kfree(dev);
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return NULL;
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}
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err = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
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if (err)
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pr_err("Failed to set SoC DMA mask: %d\n", err);
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return dev;
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}
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#endif
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/*
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* This finishes bus initialization doing things that were not possible without
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* kmalloc. Make sure to call it late enough (after mm_init).
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@ -183,6 +208,10 @@ void __init bcm47xx_bus_setup(void)
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if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_BCMA) {
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int err;
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bcm47xx_bus.bcma.dev = bcm47xx_setup_device();
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if (!bcm47xx_bus.bcma.dev)
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panic("Failed to setup SoC device\n");
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err = bcma_host_soc_init(&bcm47xx_bus.bcma);
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if (err)
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panic("Failed to initialize BCMA bus (err %d)", err);
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@ -235,6 +264,8 @@ static int __init bcm47xx_register_bus_complete(void)
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#endif
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#ifdef CONFIG_BCM47XX_BCMA
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case BCM47XX_BUS_TYPE_BCMA:
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if (device_register(bcm47xx_bus.bcma.dev))
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pr_err("Failed to register SoC device\n");
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bcma_bus_register(&bcm47xx_bus.bcma.bus);
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break;
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#endif
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@ -98,7 +98,7 @@ static void octeon_kexec_smp_down(void *ignored)
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" sync \n"
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" synci ($0) \n");
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relocated_kexec_smp_wait(NULL);
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kexec_reboot();
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}
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#endif
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@ -66,6 +66,7 @@ CONFIG_SERIAL_8250_CONSOLE=y
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# CONFIG_SERIAL_8250_PCI is not set
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CONFIG_SERIAL_8250_NR_UARTS=1
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CONFIG_SERIAL_8250_RUNTIME_UARTS=1
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CONFIG_SERIAL_OF_PLATFORM=y
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CONFIG_SERIAL_AR933X=y
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CONFIG_SERIAL_AR933X_CONSOLE=y
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# CONFIG_HW_RANDOM is not set
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@ -18,8 +18,6 @@
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#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32)
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#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
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#define MIPS_CPU_TIMER_IRQ 7
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#define MAX_IM 5
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#endif /* _FALCON_IRQ__ */
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@ -19,8 +19,6 @@
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#define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0)
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#define MIPS_CPU_TIMER_IRQ 7
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#define MAX_IM 5
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#endif
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@ -74,14 +74,15 @@ static int __init vdma_init(void)
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get_order(VDMA_PGTBL_SIZE));
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BUG_ON(!pgtbl);
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dma_cache_wback_inv((unsigned long)pgtbl, VDMA_PGTBL_SIZE);
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pgtbl = (VDMA_PGTBL_ENTRY *)KSEG1ADDR(pgtbl);
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pgtbl = (VDMA_PGTBL_ENTRY *)CKSEG1ADDR((unsigned long)pgtbl);
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/*
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* Clear the R4030 translation table
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*/
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vdma_pgtbl_init();
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r4030_write_reg32(JAZZ_R4030_TRSTBL_BASE, CPHYSADDR(pgtbl));
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r4030_write_reg32(JAZZ_R4030_TRSTBL_BASE,
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CPHYSADDR((unsigned long)pgtbl));
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r4030_write_reg32(JAZZ_R4030_TRSTBL_LIM, VDMA_PGTBL_SIZE);
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r4030_write_reg32(JAZZ_R4030_TRSTBL_INV, 0);
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@ -224,9 +224,11 @@ static struct irq_chip ltq_eiu_type = {
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.irq_set_type = ltq_eiu_settype,
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};
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static void ltq_hw_irqdispatch(int module)
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static void ltq_hw_irq_handler(struct irq_desc *desc)
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{
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int module = irq_desc_get_irq(desc) - 2;
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u32 irq;
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int hwirq;
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irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
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if (irq == 0)
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@ -237,7 +239,8 @@ static void ltq_hw_irqdispatch(int module)
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* other bits might be bogus
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*/
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irq = __fls(irq);
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do_IRQ((int)irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module));
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hwirq = irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module);
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generic_handle_irq(irq_linear_revmap(ltq_domain, hwirq));
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/* if this is a EBU irq, we need to ack it or get a deadlock */
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if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
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LTQ_EBU_PCC_ISTAT);
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}
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#define DEFINE_HWx_IRQDISPATCH(x) \
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static void ltq_hw ## x ## _irqdispatch(void) \
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{ \
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ltq_hw_irqdispatch(x); \
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}
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DEFINE_HWx_IRQDISPATCH(0)
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DEFINE_HWx_IRQDISPATCH(1)
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DEFINE_HWx_IRQDISPATCH(2)
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DEFINE_HWx_IRQDISPATCH(3)
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DEFINE_HWx_IRQDISPATCH(4)
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#if MIPS_CPU_TIMER_IRQ == 7
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static void ltq_hw5_irqdispatch(void)
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{
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do_IRQ(MIPS_CPU_TIMER_IRQ);
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}
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#else
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DEFINE_HWx_IRQDISPATCH(5)
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#endif
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static void ltq_hw_irq_handler(struct irq_desc *desc)
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{
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ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2);
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
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int irq;
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if (!pending) {
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spurious_interrupt();
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return;
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}
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pending >>= CAUSEB_IP;
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while (pending) {
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irq = fls(pending) - 1;
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do_IRQ(MIPS_CPU_IRQ_BASE + irq);
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pending &= ~BIT(irq);
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}
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}
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static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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{
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struct irq_chip *chip = <q_irq_type;
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for (i = 0; i < MAX_IM; i++)
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irq_set_chained_handler(i + 2, ltq_hw_irq_handler);
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if (cpu_has_vint) {
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pr_info("Setting up vectored interrupts\n");
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set_vi_handler(2, ltq_hw0_irqdispatch);
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set_vi_handler(3, ltq_hw1_irqdispatch);
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set_vi_handler(4, ltq_hw2_irqdispatch);
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set_vi_handler(5, ltq_hw3_irqdispatch);
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set_vi_handler(6, ltq_hw4_irqdispatch);
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set_vi_handler(7, ltq_hw5_irqdispatch);
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}
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ltq_domain = irq_domain_add_linear(node,
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(MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
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&irq_domain_ops, 0);
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#ifndef CONFIG_MIPS_MT_SMP
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set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
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IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
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#else
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set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
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IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
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#endif
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/* tell oprofile which irq to use */
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ltq_perfcount_irq = irq_create_mapping(ltq_domain, LTQ_PERF_IRQ);
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/*
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* if the timer irq is not one of the mips irqs we need to
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* create a mapping
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*/
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if (MIPS_CPU_TIMER_IRQ != 7)
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irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ);
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/* the external interrupts are optional and xway only */
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eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
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if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
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unsigned int get_c0_compare_int(void)
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{
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return MIPS_CPU_TIMER_IRQ;
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return CP0_LEGACY_COMPARE_IRQ;
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}
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static struct of_device_id __initdata of_irq_ids[] = {
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@ -369,7 +369,9 @@ int __init octeon_msi_initialize(void)
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int irq;
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struct irq_chip *msi;
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if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE) {
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if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_INVALID) {
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return 0;
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} else if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE) {
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msi_rcv_reg[0] = CVMX_PEXP_NPEI_MSI_RCV0;
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msi_rcv_reg[1] = CVMX_PEXP_NPEI_MSI_RCV1;
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msi_rcv_reg[2] = CVMX_PEXP_NPEI_MSI_RCV2;
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@ -6,6 +6,7 @@
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struct bcma_soc {
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struct bcma_bus bus;
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struct device *dev;
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};
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int __init bcma_host_soc_register(struct bcma_soc *soc);
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