i.MX fixes for 6.4, round 2:

- Fix SPI CS pinmux for the final production version of imx8mn-beacon
   board.
 - Fix GPIOs for USDHC2 CD and WP signals on imx8qm-mek board.
 - Assign default clock rate for i.MX8 LPUARTs to fix UART failure.
 -----BEGIN PGP SIGNATURE-----
 
 iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmSAj+8UHHNoYXduZ3Vv
 QGtlcm5lbC5vcmcACgkQUFdYWoewfM4UbQf8CZyNR0LC443TKq24tV5YFQktQOc4
 4FD7H0oYnqcnlAgxqo0X2aq4K+OwpWxwN4sqKFq3IT6U/FbPxpNIAUXIFjCdvUQs
 rnvOmsJRgW+RSc+imVfgKfDPQG3bPX6YaZ2G8b1IyP3HrPfpOgi0V5G5Oi/rzSJ+
 doP/pvzNKbS+pUp2ez+LD/YfbcPJcJ6ALX5IkJ1oPbhM7OSpsaenoi1KrlYIC/f0
 PLzGnRSu6XAv+Oq7HZz4RWehdWmdXZaAaeHqMID5iDoaELgsqS8hs5C01N0s898U
 qyK5va0o9uKfN564ViBSHkrjvIBCRpujap6Mi/56alQxIg7UixmjFgBc3A==
 =AbVA
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmSDF98ACgkQYKtH/8kJ
 UieJSxAA1RWlEnhdJCapWooFiuZvSG5W4ZysRq7ni6rkxzbD3IcylYCzLmhM4/bh
 QOHvtKJDNe93R8mASU8mbSCnx1cvesVJzjBwPw5qnbnRkiNvQGVg8wU2cxSQ8Tph
 XHBUOP3fiBRO/9r6N7ffdtYP4A9tH3Oo59vwRv6GgnMCzoRidIk4eDrIXYCZ0RHh
 6d93zsFzmBSIca+qokF7nzSwWDSX6UbComIy5sowr2DBo9doJfBrih2tmNEYEo/d
 ecvFQoNYxtq0MJnhlYPnx2xYz6b68vF6KzRE0bx6WL2aynFJL0MT8WcBYnDCTJhG
 vhyO7tAI/pso6qKmrJA3uVAEeDPh3CYyv5KuTWCeAuhZJr9AjsZ3kEiOoQNduM8O
 agN6hFgjknekiBvoY4ej2PnVqhTSf2IMuAO8rEJld9d0SIs4r7z1ok54yI9s0OEP
 FaIwvCWF7LlyEx2734JUKAkEumn34g6V+skasFlSyF4V0qo5+7gLekMqH5KrWYZ7
 4e0Sbi5nhpqrNNAuUy7l8scaoPBC8F5YLgpgUW5fdkqIzfk1PfMIRkd3AoRXU1bX
 4Y97MhB5Z1Lw/3065iWwdiPzwQBkuEfr+vjd+0E0LudJBDvBykieD+iRv5EXxVV0
 wRmerups5UhKpoPBJpGr6CJ3hBaOVWdu4yacuGXNIcLTEBEoX4w=
 =n8fu
 -----END PGP SIGNATURE-----

Merge tag 'imx-fixes-6.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes

i.MX fixes for 6.4, round 2:

- Fix SPI CS pinmux for the final production version of imx8mn-beacon
  board.
- Fix GPIOs for USDHC2 CD and WP signals on imx8qm-mek board.
- Assign default clock rate for i.MX8 LPUARTs to fix UART failure.

* tag 'imx-fixes-6.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: imx8mn-beacon: Fix SPI CS pinmux
  arm64: dts: imx8-ss-dma: assign default clock rate for lpuarts
  arm64: dts: imx8qm-mek: correct GPIOs for USDHC2 CD and WP signals

Link: https://lore.kernel.org/r/20230607141312.GU4199@dragon
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-06-09 14:15:18 +02:00
commit 5cdd5ec176
3 changed files with 12 additions and 4 deletions

View file

@ -90,6 +90,8 @@ lpuart0: serial@5a060000 {
clocks = <&uart0_lpcg IMX_LPCG_CLK_4>,
<&uart0_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_0>;
status = "disabled";
};
@ -100,6 +102,8 @@ lpuart1: serial@5a070000 {
clocks = <&uart1_lpcg IMX_LPCG_CLK_4>,
<&uart1_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_1>;
status = "disabled";
};
@ -110,6 +114,8 @@ lpuart2: serial@5a080000 {
clocks = <&uart2_lpcg IMX_LPCG_CLK_4>,
<&uart2_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_2>;
status = "disabled";
};
@ -120,6 +126,8 @@ lpuart3: serial@5a090000 {
clocks = <&uart3_lpcg IMX_LPCG_CLK_4>,
<&uart3_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_3>;
status = "disabled";
};

View file

@ -81,7 +81,7 @@ sound {
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_espi2>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
eeprom@0 {
@ -202,7 +202,7 @@ pinctrl_espi2: espi2grp {
MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41
MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x41
>;
};

View file

@ -82,8 +82,8 @@ &usdhc2 {
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>;
wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
status = "okay";
};