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drm/amd/powerplay: Set higher SCLK&MCLK frequency than dpm7 in OD (v2)

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Fix the issue that SCLK&MCLK can't be set higher than dpm7 when
OD is enabled in SMU7.

v2: fix warning (Alex)

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Acked-by: Rex Zhu<rezhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Kenneth Feng 2018-06-12 15:07:37 +08:00 committed by Alex Deucher
parent 333c8d3ef2
commit 5c16f36f6f
1 changed files with 5 additions and 2 deletions
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7
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
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@ -3755,14 +3755,17 @@ static int smu7_trim_dpm_states(struct pp_hwmgr *hwmgr,
static int smu7_generate_dpm_level_enable_mask(
struct pp_hwmgr *hwmgr, const void *input)
{
int result;
int result = 0;
const struct phm_set_power_state_input *states =
(const struct phm_set_power_state_input *)input;
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
const struct smu7_power_state *smu7_ps =
cast_const_phw_smu7_power_state(states->pnew_state);
result = smu7_trim_dpm_states(hwmgr, smu7_ps);
/*skip the trim if od is enabled*/
if (!hwmgr->od_enabled)
result = smu7_trim_dpm_states(hwmgr, smu7_ps);
if (result)
return result;