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synced 2024-10-16 00:10:42 +00:00
crypto: hisilicon/qm - fix EQ/AEQ interrupt issue
During hisilicon accelerator live migration operation. In order to
prevent the problem of EQ/AEQ interrupt loss. Migration driver will
trigger an EQ/AEQ doorbell at the end of the migration.
This operation may cause double interruption of EQ/AEQ events.
To ensure that the EQ/AEQ interrupt processing function is normal.
The interrupt handling functionality of EQ/AEQ needs to be updated.
Used to handle repeated interrupts event.
Fixes: b0eed08590
("hisi_acc_vfio_pci: Add support for VFIO live migration")
Signed-off-by: Longfang Liu <liulongfang@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
parent
ca06ef976e
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@ -894,13 +894,47 @@ static void qm_poll_req_cb(struct hisi_qp *qp)
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qm_db(qm, qp->qp_id, QM_DOORBELL_CMD_CQ, qp->qp_status.cq_head, 1);
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}
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static int qm_get_complete_eqe_num(struct hisi_qm_poll_data *poll_data)
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static void qm_work_process(struct work_struct *work)
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{
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struct hisi_qm_poll_data *poll_data =
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container_of(work, struct hisi_qm_poll_data, work);
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struct hisi_qm *qm = poll_data->qm;
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u16 eqe_num = poll_data->eqe_num;
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struct hisi_qp *qp;
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int i;
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for (i = eqe_num - 1; i >= 0; i--) {
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qp = &qm->qp_array[poll_data->qp_finish_id[i]];
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if (unlikely(atomic_read(&qp->qp_status.flags) == QP_STOP))
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continue;
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if (qp->event_cb) {
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qp->event_cb(qp);
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continue;
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}
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if (likely(qp->req_cb))
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qm_poll_req_cb(qp);
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}
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}
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static void qm_get_complete_eqe_num(struct hisi_qm *qm)
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{
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struct qm_eqe *eqe = qm->eqe + qm->status.eq_head;
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struct hisi_qm_poll_data *poll_data = NULL;
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u16 eq_depth = qm->eq_depth;
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int eqe_num = 0;
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u16 cqn;
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u16 cqn, eqe_num = 0;
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if (QM_EQE_PHASE(eqe) != qm->status.eqc_phase) {
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atomic64_inc(&qm->debug.dfx.err_irq_cnt);
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qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);
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return;
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}
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cqn = le32_to_cpu(eqe->dw0) & QM_EQE_CQN_MASK;
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if (unlikely(cqn >= qm->qp_num))
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return;
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poll_data = &qm->poll_data[cqn];
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while (QM_EQE_PHASE(eqe) == qm->status.eqc_phase) {
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cqn = le32_to_cpu(eqe->dw0) & QM_EQE_CQN_MASK;
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@ -920,69 +954,19 @@ static int qm_get_complete_eqe_num(struct hisi_qm_poll_data *poll_data)
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break;
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}
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poll_data->eqe_num = eqe_num;
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queue_work(qm->wq, &poll_data->work);
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qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);
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return eqe_num;
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}
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static void qm_work_process(struct work_struct *work)
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{
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struct hisi_qm_poll_data *poll_data =
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container_of(work, struct hisi_qm_poll_data, work);
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struct hisi_qm *qm = poll_data->qm;
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struct hisi_qp *qp;
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int eqe_num, i;
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/* Get qp id of completed tasks and re-enable the interrupt. */
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eqe_num = qm_get_complete_eqe_num(poll_data);
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for (i = eqe_num - 1; i >= 0; i--) {
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qp = &qm->qp_array[poll_data->qp_finish_id[i]];
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if (unlikely(atomic_read(&qp->qp_status.flags) == QP_STOP))
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continue;
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if (qp->event_cb) {
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qp->event_cb(qp);
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continue;
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}
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if (likely(qp->req_cb))
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qm_poll_req_cb(qp);
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}
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}
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static bool do_qm_eq_irq(struct hisi_qm *qm)
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{
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struct qm_eqe *eqe = qm->eqe + qm->status.eq_head;
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struct hisi_qm_poll_data *poll_data;
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u16 cqn;
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if (!readl(qm->io_base + QM_VF_EQ_INT_SOURCE))
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return false;
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if (QM_EQE_PHASE(eqe) == qm->status.eqc_phase) {
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cqn = le32_to_cpu(eqe->dw0) & QM_EQE_CQN_MASK;
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poll_data = &qm->poll_data[cqn];
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queue_work(qm->wq, &poll_data->work);
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return true;
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}
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return false;
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}
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static irqreturn_t qm_eq_irq(int irq, void *data)
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{
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struct hisi_qm *qm = data;
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bool ret;
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ret = do_qm_eq_irq(qm);
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if (ret)
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return IRQ_HANDLED;
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/* Get qp id of completed tasks and re-enable the interrupt */
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qm_get_complete_eqe_num(qm);
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atomic64_inc(&qm->debug.dfx.err_irq_cnt);
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qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);
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return IRQ_NONE;
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return IRQ_HANDLED;
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}
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static irqreturn_t qm_mb_cmd_irq(int irq, void *data)
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@ -1064,6 +1048,8 @@ static irqreturn_t qm_aeq_thread(int irq, void *data)
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u16 aeq_depth = qm->aeq_depth;
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u32 type, qp_id;
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atomic64_inc(&qm->debug.dfx.aeq_irq_cnt);
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while (QM_AEQE_PHASE(aeqe) == qm->status.aeqc_phase) {
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type = (le32_to_cpu(aeqe->dw0) >> QM_AEQE_TYPE_SHIFT) &
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QM_AEQE_TYPE_MASK;
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@ -1102,17 +1088,6 @@ static irqreturn_t qm_aeq_thread(int irq, void *data)
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return IRQ_HANDLED;
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}
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static irqreturn_t qm_aeq_irq(int irq, void *data)
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{
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struct hisi_qm *qm = data;
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atomic64_inc(&qm->debug.dfx.aeq_irq_cnt);
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if (!readl(qm->io_base + QM_VF_AEQ_INT_SOURCE))
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return IRQ_NONE;
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return IRQ_WAKE_THREAD;
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}
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static void qm_init_qp_status(struct hisi_qp *qp)
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{
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struct hisi_qp_status *qp_status = &qp->qp_status;
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@ -4923,8 +4898,8 @@ static int qm_register_aeq_irq(struct hisi_qm *qm)
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return 0;
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irq_vector = val & QM_IRQ_VECTOR_MASK;
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ret = request_threaded_irq(pci_irq_vector(pdev, irq_vector), qm_aeq_irq,
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qm_aeq_thread, 0, qm->dev_name, qm);
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ret = request_threaded_irq(pci_irq_vector(pdev, irq_vector), NULL,
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qm_aeq_thread, IRQF_ONESHOT, qm->dev_name, qm);
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if (ret)
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dev_err(&pdev->dev, "failed to request eq irq, ret = %d", ret);
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@ -276,6 +276,7 @@ struct hisi_qm_poll_data {
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struct hisi_qm *qm;
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struct work_struct work;
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u16 *qp_finish_id;
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u16 eqe_num;
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};
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/**
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