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KVM: arm/arm64: vgic-new: Add GICv3 IDREGS register handler

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We implement the only one ID register that is required by the
architecture, also this is the one that Linux actually checks.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
This commit is contained in:
Andre Przywara 2016-01-22 18:18:52 +00:00 committed by Christoffer Dall
parent 741972d8a6
commit 54f59d2b3a
1 changed files with 14 additions and 2 deletions
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16
virt/kvm/arm/vgic/vgic-mmio-v3.c
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@ -96,6 +96,18 @@ static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu,
return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0); return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
} }
static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
gpa_t addr, unsigned int len)
{
switch (addr & 0xffff) {
case GICD_PIDR2:
/* report a GICv3 compliant implementation */
return 0x3b;
}
return 0;
}
/* /*
* The GICv3 per-IRQ registers are split to control PPIs and SGIs in the * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
* redistributors, while SPIs are covered by registers in the distributor * redistributors, while SPIs are covered by registers in the distributor
@ -161,7 +173,7 @@ static const struct vgic_register_region vgic_v3_dist_registers[] = {
vgic_mmio_read_raz, vgic_mmio_write_wi, 64, vgic_mmio_read_raz, vgic_mmio_write_wi, 64,
VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
REGISTER_DESC_WITH_LENGTH(GICD_IDREGS, REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
vgic_mmio_read_raz, vgic_mmio_write_wi, 48, vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
VGIC_ACCESS_32bit), VGIC_ACCESS_32bit),
}; };
@ -182,7 +194,7 @@ static const struct vgic_register_region vgic_v3_rdbase_registers[] = {
vgic_mmio_read_raz, vgic_mmio_write_wi, 8, vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
REGISTER_DESC_WITH_LENGTH(GICR_IDREGS, REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
vgic_mmio_read_raz, vgic_mmio_write_wi, 48, vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
VGIC_ACCESS_32bit), VGIC_ACCESS_32bit),
}; };