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staging: comedi: hwdrv_apci1500: introduce z8536_read()
The Z8536 CIO registers are indirectly read by writing the register offset to the control register then reading the control register to get the value. Introduce a helper function to read the Z8536 CIO registers. The registers are read from "normal" code and in the interrupt handler, spinlock the sequence to protect the indirect register access. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
Greg Kroah-Hartman
parent
b7392d2247
commit
54c3ef4657
1 changed files with 58 additions and 164 deletions
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@ -129,6 +129,20 @@ static int i_InputChannel;
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static int i_TimerCounter1Enabled, i_TimerCounter2Enabled,
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i_WatchdogCounter3Enabled;
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static unsigned int z8536_read(struct comedi_device *dev, unsigned int reg)
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{
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struct apci1500_private *devpriv = dev->private;
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unsigned long flags;
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unsigned int val;
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spin_lock_irqsave(&dev->spinlock, flags);
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outb(reg, devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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val = inb(devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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spin_unlock_irqrestore(&dev->spinlock, flags);
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return val;
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}
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/*
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* An event can be generated for each port. The first event is related to the
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* first 8 channels (port 1) and the second to the following 6 channels (port 2)
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@ -311,14 +325,8 @@ static int apci1500_di_config(struct comedi_device *dev,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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/* Selects the mode specification mask */
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/* register of port 1 */
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outb(APCI1500_RW_PORT_A_SPECIFICATION,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue =
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inb(devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue = z8536_read(dev,
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APCI1500_RW_PORT_A_SPECIFICATION);
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/* Selects the mode specification mask */
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/* register of port 1 */
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@ -366,14 +374,8 @@ static int apci1500_di_config(struct comedi_device *dev,
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outb(0x74,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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/* Selects the mode specification mask */
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/* register of port B */
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outb(APCI1500_RW_PORT_B_SPECIFICATION,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue =
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inb(devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue = z8536_read(dev,
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APCI1500_RW_PORT_B_SPECIFICATION);
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/* Selects the mode specification mask */
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/* register of port B */
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@ -416,14 +418,8 @@ static int apci1500_di_config(struct comedi_device *dev,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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/* Selects the mode specification mask */
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/* register of port 2 */
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outb(APCI1500_RW_PORT_B_SPECIFICATION,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue =
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inb(devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue = z8536_read(dev,
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APCI1500_RW_PORT_B_SPECIFICATION);
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/* Selects the mode specification mask */
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/* register of port 2 */
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outb(APCI1500_RW_PORT_B_SPECIFICATION,
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@ -500,12 +496,8 @@ static int apci1500_di_write(struct comedi_device *dev,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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i_Event1InterruptStatus = 1;
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outb(APCI1500_RW_PORT_A_SPECIFICATION,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue =
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inb(devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue = z8536_read(dev,
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APCI1500_RW_PORT_A_SPECIFICATION);
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/* Selects the master interrupt control register */
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outb(APCI1500_RW_MASTER_INTERRUPT_CONTROL, devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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@ -1068,17 +1060,8 @@ static int apci1500_timer_config(struct comedi_device *dev,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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/* Selects the master configuration register */
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outb(APCI1500_RW_MASTER_CONFIGURATION_CONTROL,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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/* Reads the register */
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i_MasterConfiguration =
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inb(devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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i_MasterConfiguration = z8536_read(dev,
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APCI1500_RW_MASTER_CONFIGURATION_CONTROL);
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/* Enables timer/counter 1 and triggers timer/counter 1 */
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@ -1228,17 +1211,8 @@ static int apci1500_timer_config(struct comedi_device *dev,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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/* Selects the master configuration register */
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outb(APCI1500_RW_MASTER_CONFIGURATION_CONTROL,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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/* Reads the register */
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i_MasterConfiguration =
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inb(devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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i_MasterConfiguration = z8536_read(dev,
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APCI1500_RW_MASTER_CONFIGURATION_CONTROL);
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/* Enables timer/counter 2 and triggers timer/counter 2 */
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@ -1382,17 +1356,8 @@ static int apci1500_timer_config(struct comedi_device *dev,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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/* Selects the master configuration register */
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outb(APCI1500_RW_MASTER_CONFIGURATION_CONTROL,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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/* Reads the register */
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i_MasterConfiguration =
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inb(devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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i_MasterConfiguration = z8536_read(dev,
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APCI1500_RW_MASTER_CONFIGURATION_CONTROL);
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/* Enables watchdog/counter 3 and triggers watchdog/counter 3 */
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@ -1756,21 +1721,12 @@ static int apci1500_timer_bits(struct comedi_device *dev,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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/* Selects the counter register (high) */
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outb(APCI1500_R_CPT_TMR1_VALUE_HIGH,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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data[0] =
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inb(devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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data[0] = z8536_read(dev,
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APCI1500_R_CPT_TMR1_VALUE_HIGH);
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data[0] = data[0] << 8;
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data[0] = data[0] & 0xff00;
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outb(APCI1500_R_CPT_TMR1_VALUE_LOW,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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data[0] =
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data[0] | inb(devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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data[0] |= z8536_read(dev,
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APCI1500_R_CPT_TMR1_VALUE_LOW);
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} else {
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dev_warn(dev->class_dev,
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"Timer/Counter1 not configured\n");
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@ -1798,21 +1754,12 @@ static int apci1500_timer_bits(struct comedi_device *dev,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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/* Selects the counter register (high) */
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outb(APCI1500_R_CPT_TMR2_VALUE_HIGH,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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data[0] =
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inb(devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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data[0] = z8536_read(dev,
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APCI1500_R_CPT_TMR2_VALUE_HIGH);
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data[0] = data[0] << 8;
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data[0] = data[0] & 0xff00;
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outb(APCI1500_R_CPT_TMR2_VALUE_LOW,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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data[0] =
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data[0] | inb(devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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data[0] |= z8536_read(dev,
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APCI1500_R_CPT_TMR2_VALUE_LOW);
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} else {
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dev_warn(dev->class_dev,
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"Timer/Counter2 not configured\n");
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@ -1840,21 +1787,12 @@ static int apci1500_timer_bits(struct comedi_device *dev,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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/* Selects the counter register (high) */
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outb(APCI1500_R_CPT_TMR3_VALUE_HIGH,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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data[0] =
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inb(devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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data[0] = z8536_read(dev,
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APCI1500_R_CPT_TMR3_VALUE_HIGH);
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data[0] = data[0] << 8;
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data[0] = data[0] & 0xff00;
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outb(APCI1500_R_CPT_TMR3_VALUE_LOW,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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data[0] =
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data[0] | inb(devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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data[0] |= z8536_read(dev,
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APCI1500_R_CPT_TMR3_VALUE_LOW);
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} else {
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dev_warn(dev->class_dev,
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"WatchdogCounter3 not configured\n");
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@ -1914,10 +1852,7 @@ static int apci1500_do_bits(struct comedi_device *dev,
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}
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}
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/* Selects the mode specification register of port B */
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outb(APCI1500_RW_PORT_B_SPECIFICATION,
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devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue = inb(devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue = z8536_read(dev, APCI1500_RW_PORT_B_SPECIFICATION);
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outb(APCI1500_RW_PORT_B_SPECIFICATION,
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devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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/* Writes the new configuration (APCI1500_OR) */
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@ -1942,20 +1877,14 @@ static int apci1500_do_bits(struct comedi_device *dev,
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devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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outb(i_Constant, devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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/* Selects the command and status register of port A */
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outb(APCI1500_RW_PORT_A_COMMAND_AND_STATUS,
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devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue = inb(devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue = z8536_read(dev, APCI1500_RW_PORT_A_COMMAND_AND_STATUS);
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outb(APCI1500_RW_PORT_A_COMMAND_AND_STATUS,
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devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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/* Deletes the interrupt of port A */
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i_RegValue = (i_RegValue & 0x0F) | 0x20;
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outb(i_RegValue, devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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/* Selects the command and status register of port B */
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outb(APCI1500_RW_PORT_B_COMMAND_AND_STATUS,
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devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue = inb(devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue = z8536_read(dev, APCI1500_RW_PORT_B_COMMAND_AND_STATUS);
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outb(APCI1500_RW_PORT_B_COMMAND_AND_STATUS,
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devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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/* Deletes the interrupt of port B */
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@ -1963,10 +1892,7 @@ static int apci1500_do_bits(struct comedi_device *dev,
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i_RegValue = (i_RegValue & 0x0F) | 0x20;
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outb(i_RegValue, devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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/* Selects the command and status register of timer 1 */
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outb(APCI1500_RW_CPT_TMR1_CMD_STATUS,
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devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue = inb(devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue = z8536_read(dev, APCI1500_RW_CPT_TMR1_CMD_STATUS);
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outb(APCI1500_RW_CPT_TMR1_CMD_STATUS,
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devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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/* Deletes the interrupt of timer 1 */
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@ -1974,10 +1900,7 @@ static int apci1500_do_bits(struct comedi_device *dev,
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i_RegValue = (i_RegValue & 0x0F) | 0x20;
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outb(i_RegValue, devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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/* Selects the command and status register of timer 2 */
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outb(APCI1500_RW_CPT_TMR2_CMD_STATUS,
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devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue = inb(devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue = z8536_read(dev, APCI1500_RW_CPT_TMR2_CMD_STATUS);
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outb(APCI1500_RW_CPT_TMR2_CMD_STATUS,
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devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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/* Deletes the interrupt of timer 2 */
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@ -1985,10 +1908,7 @@ static int apci1500_do_bits(struct comedi_device *dev,
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i_RegValue = (i_RegValue & 0x0F) | 0x20;
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outb(i_RegValue, devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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/* Selects the command and status register of timer 3 */
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outb(APCI1500_RW_CPT_TMR3_CMD_STATUS,
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devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue = inb(devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue = z8536_read(dev, APCI1500_RW_CPT_TMR3_CMD_STATUS);
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outb(APCI1500_RW_CPT_TMR3_CMD_STATUS,
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devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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/* Deletes the interrupt of timer 3 */
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@ -2030,11 +1950,8 @@ static irqreturn_t apci1500_interrupt(int irq, void *d)
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/* Disable all Interrupt */
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/* Selects the master interrupt control register */
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/* Disables the main interrupt on the board */
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/* Selects the command and status register of port A */
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outb(APCI1500_RW_PORT_A_COMMAND_AND_STATUS,
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devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue =
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inb(devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue = z8536_read(dev,
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APCI1500_RW_PORT_A_COMMAND_AND_STATUS);
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if ((i_RegValue & 0x60) == 0x60) {
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/* Selects the command and status register of port A */
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outb(APCI1500_RW_PORT_A_COMMAND_AND_STATUS,
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@ -2047,20 +1964,11 @@ static irqreturn_t apci1500_interrupt(int irq, void *d)
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APCI1500_Z8536_CONTROL_REGISTER);
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i_InterruptMask = i_InterruptMask | 1;
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if (i_Logic == APCI1500_OR_PRIORITY) {
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outb(APCI1500_RW_PORT_A_SPECIFICATION,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue =
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inb(devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue = z8536_read(dev,
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APCI1500_RW_PORT_A_SPECIFICATION);
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/* Selects the interrupt vector register of port A */
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outb(APCI1500_RW_PORT_A_INTERRUPT_CONTROL,
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devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue =
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inb(devpriv->iobase +
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APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue = z8536_read(dev,
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APCI1500_RW_PORT_A_INTERRUPT_CONTROL);
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i_InputChannel = 1 + (i_RegValue >> 1);
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@ -2069,11 +1977,8 @@ static irqreturn_t apci1500_interrupt(int irq, void *d)
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}
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}
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/* Selects the command and status register of port B */
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outb(APCI1500_RW_PORT_B_COMMAND_AND_STATUS,
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devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue =
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inb(devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue = z8536_read(dev,
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APCI1500_RW_PORT_B_COMMAND_AND_STATUS);
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if ((i_RegValue & 0x60) == 0x60) {
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/* Selects the command and status register of port B */
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outb(APCI1500_RW_PORT_B_COMMAND_AND_STATUS,
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@ -2111,11 +2016,7 @@ static irqreturn_t apci1500_interrupt(int irq, void *d)
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}
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}
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/* Selects the command and status register of timer 1 */
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outb(APCI1500_RW_CPT_TMR1_CMD_STATUS,
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devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue =
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inb(devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
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i_RegValue = z8536_read(dev, APCI1500_RW_CPT_TMR1_CMD_STATUS);
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if ((i_RegValue & 0x60) == 0x60) {
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/* Selects the command and status register of timer 1 */
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outb(APCI1500_RW_CPT_TMR1_CMD_STATUS,
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@ -2128,11 +2029,8 @@ static irqreturn_t apci1500_interrupt(int irq, void *d)
|
|||
APCI1500_Z8536_CONTROL_REGISTER);
|
||||
i_InterruptMask = i_InterruptMask | 4;
|
||||
}
|
||||
/* Selects the command and status register of timer 2 */
|
||||
outb(APCI1500_RW_CPT_TMR2_CMD_STATUS,
|
||||
devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
|
||||
i_RegValue =
|
||||
inb(devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
|
||||
|
||||
i_RegValue = z8536_read(dev, APCI1500_RW_CPT_TMR2_CMD_STATUS);
|
||||
if ((i_RegValue & 0x60) == 0x60) {
|
||||
/* Selects the command and status register of timer 2 */
|
||||
outb(APCI1500_RW_CPT_TMR2_CMD_STATUS,
|
||||
|
|
@ -2146,11 +2044,7 @@ static irqreturn_t apci1500_interrupt(int irq, void *d)
|
|||
i_InterruptMask = i_InterruptMask | 8;
|
||||
}
|
||||
|
||||
/* Selects the command and status register of timer 3 */
|
||||
outb(APCI1500_RW_CPT_TMR3_CMD_STATUS,
|
||||
devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
|
||||
i_RegValue =
|
||||
inb(devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
|
||||
i_RegValue = z8536_read(dev, APCI1500_RW_CPT_TMR3_CMD_STATUS);
|
||||
if ((i_RegValue & 0x60) == 0x60) {
|
||||
/* Selects the command and status register of timer 3 */
|
||||
outb(APCI1500_RW_CPT_TMR3_CMD_STATUS,
|
||||
|
|
|
|||
Loading…
Reference in a new issue