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x86/msr: Move ARCH_CAP_XAPIC_DISABLE bit definition to its rightful place
The ARCH_CAP_XAPIC_DISABLE bit of MSR_IA32_ARCH_CAP is not in the correct sorted order. Move it where it belongs. No functional change. [ bp: Massage commit message. ] Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/243317ff6c8db307b7701a45f71e5c21da80194b.1705632532.git.pawan.kumar.gupta@linux.intel.com
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@ -163,6 +163,10 @@
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* are restricted to targets in
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* kernel.
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*/
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#define ARCH_CAP_XAPIC_DISABLE BIT(21) /*
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* IA32_XAPIC_DISABLE_STATUS MSR
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* supported
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*/
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#define ARCH_CAP_PBRSB_NO BIT(24) /*
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* Not susceptible to Post-Barrier
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* Return Stack Buffer Predictions.
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@ -185,11 +189,6 @@
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* File.
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*/
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#define ARCH_CAP_XAPIC_DISABLE BIT(21) /*
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* IA32_XAPIC_DISABLE_STATUS MSR
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* supported
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*/
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#define MSR_IA32_FLUSH_CMD 0x0000010b
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#define L1D_FLUSH BIT(0) /*
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* Writeback and invalidate the
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