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x86/cpufeatures: Add the CPU feature bit for FRED
Any FRED enabled CPU will always have the following features as its baseline: 1) LKGS, load attributes of the GS segment but the base address into the IA32_KERNEL_GS_BASE MSR instead of the GS segment’s descriptor cache. 2) WRMSRNS, non-serializing WRMSR for faster MSR writes. Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com> Signed-off-by: Xin Li <xin3.li@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Shan Kang <shan.kang@intel.com> Link: https://lore.kernel.org/r/20231205105030.8698-7-xin3.li@intel.com
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@ -326,6 +326,7 @@
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#define X86_FEATURE_FZRM (12*32+10) /* "" Fast zero-length REP MOVSB */
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#define X86_FEATURE_FSRS (12*32+11) /* "" Fast short REP STOSB */
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#define X86_FEATURE_FSRC (12*32+12) /* "" Fast short REP {CMPSB,SCASB} */
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#define X86_FEATURE_FRED (12*32+17) /* Flexible Return and Event Delivery */
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#define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */
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#define X86_FEATURE_WRMSRNS (12*32+19) /* "" Non-serializing WRMSR */
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#define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */
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@ -82,6 +82,8 @@ static const struct cpuid_dep cpuid_deps[] = {
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{ X86_FEATURE_XFD, X86_FEATURE_XGETBV1 },
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{ X86_FEATURE_AMX_TILE, X86_FEATURE_XFD },
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{ X86_FEATURE_SHSTK, X86_FEATURE_XSAVES },
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{ X86_FEATURE_FRED, X86_FEATURE_LKGS },
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{ X86_FEATURE_FRED, X86_FEATURE_WRMSRNS },
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{}
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};
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@ -321,6 +321,7 @@
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#define X86_FEATURE_FZRM (12*32+10) /* "" Fast zero-length REP MOVSB */
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#define X86_FEATURE_FSRS (12*32+11) /* "" Fast short REP STOSB */
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#define X86_FEATURE_FSRC (12*32+12) /* "" Fast short REP {CMPSB,SCASB} */
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#define X86_FEATURE_FRED (12*32+17) /* Flexible Return and Event Delivery */
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#define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */
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#define X86_FEATURE_WRMSRNS (12*32+19) /* "" Non-serializing WRMSR */
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#define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */
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