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RISC-V Patches for the 6.5 Merge Window, Part 2

Browse source 
* A bunch of fixes/cleanups from the first part of the merge window,
   mostly related to ACPI and vector as those were large.
 * Some documentation improvements, mostly related to the new code.
 * The "riscv,isa" DT key is deprecated.
 * Support for link-time dead code elimination.
 * Support for minor fault registration in userfaultd.
 * A handful of cleanups around CMO alternatives.
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Merge tag 'riscv-for-linus-6.5-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull more RISC-V updates from Palmer Dabbelt:

 - A bunch of fixes/cleanups from the first part of the merge window,
   mostly related to ACPI and vector as those were large

 - Some documentation improvements, mostly related to the new code

 - The "riscv,isa" DT key is deprecated

 - Support for link-time dead code elimination

 - Support for minor fault registration in userfaultd

 - A handful of cleanups around CMO alternatives

* tag 'riscv-for-linus-6.5-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (23 commits)
  riscv: mm: mark noncoherent_supported as __ro_after_init
  riscv: mm: mark CBO relate initialization funcs as __init
  riscv: errata: thead: only set cbom size & noncoherent during boot
  riscv: Select HAVE_ARCH_USERFAULTFD_MINOR
  RISC-V: Document the ISA string parsing rules for ACPI
  risc-v: Fix order of IPI enablement vs RCU startup
  mm: riscv: fix an unsafe pte read in huge_pte_alloc()
  dt-bindings: riscv: deprecate riscv,isa
  RISC-V: drop error print from riscv_hartid_to_cpuid()
  riscv: Discard vector state on syscalls
  riscv: move memblock_allow_resize() after linear mapping is ready
  riscv: Enable ARCH_SUSPEND_POSSIBLE for s2idle
  riscv: vdso: include vdso/vsyscall.h for vdso_data
  selftests: Test RISC-V Vector's first-use handler
  riscv: vector: clear V-reg in the first-use trap
  riscv: vector: only enable interrupts in the first-use trap
  RISC-V: Fix up some vector state related build failures
  RISC-V: Document that V registers are clobbered on syscalls
  riscv: disable HAVE_LD_DEAD_CODE_DATA_ELIMINATION for LLD
  riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION
  ...
This commit is contained in:
Linus Torvalds 2023-07-07 10:07:19 -07:00
parent 22dcc7d77f e8605e8fdf
commit 4f6b6c2b2f
24 changed files with 450 additions and 54 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

43
Documentation/devicetree/bindings/riscv/cpus.yaml
View file

@ -25,6 +25,7 @@ description: |
allOf:
- $ref: /schemas/cpu.yaml#
- $ref: extensions.yaml
properties:
compatible:
@ -82,25 +83,6 @@ properties:
description:
The blocksize in bytes for the Zicboz cache operations.
riscv,isa:
description:
Identifies the specific RISC-V instruction set architecture
supported by the hart. These are documented in the RISC-V
User-Level ISA document, available from
https://riscv.org/specifications/
Due to revisions of the ISA specification, some deviations
have arisen over time.
Notably, riscv,isa was defined prior to the creation of the
Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i"
implies "zicntr_zicsr_zifencei_zihpm".
While the isa strings in ISA specification are case
insensitive, letters in the riscv,isa string must be all
lowercase.
$ref: /schemas/types.yaml#/definitions/string
pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
# RISC-V has multiple properties for cache op block sizes as the sizes
# differ between individual CBO extensions
cache-op-block-size: false
@ -139,8 +121,17 @@ properties:
DMIPS/MHz, relative to highest capacity-dmips-mhz
in the system.
anyOf:
- required:
- riscv,isa
- required:
- riscv,isa-base
dependencies:
riscv,isa-base: [ "riscv,isa-extensions" ]
riscv,isa-extensions: [ "riscv,isa-base" ]
required:
- riscv,isa
- interrupt-controller
unevaluatedProperties: false
@ -160,7 +151,9 @@ examples:
i-cache-sets = <128>;
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "c";
cpu_intc0: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@ -183,8 +176,10 @@ examples:
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <1>;
riscv,isa = "rv64imafdc";
tlb-split;
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
cpu_intc1: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@ -202,8 +197,10 @@ examples:
device_type = "cpu";
reg = <0>;
compatible = "riscv";
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;

250
Documentation/devicetree/bindings/riscv/extensions.yaml Normal file
View file

@ -0,0 +1,250 @@
# SPDX-License-Identifier: (GPL-2.0 OR MIT)
%YAML 1.2
---
$id: http://devicetree.org/schemas/riscv/extensions.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: RISC-V ISA extensions
maintainers:
- Paul Walmsley <paul.walmsley@sifive.com>
- Palmer Dabbelt <palmer@sifive.com>
- Conor Dooley <conor@kernel.org>
description: |
RISC-V has a large number of extensions, some of which are "standard"
extensions, meaning they are ratified by RISC-V International, and others
are "vendor" extensions.
This document defines properties that indicate whether a hart supports a
given extension.
Once a standard extension has been ratified, no changes in behaviour can be
made without the creation of a new extension.
The properties for standard extensions therefore map to their originally
ratified states, with the exception of the I, Zicntr & Zihpm extensions.
See the "i" property for more information.
select:
properties:
compatible:
contains:
const: riscv
properties:
riscv,isa:
description:
Identifies the specific RISC-V instruction set architecture
supported by the hart. These are documented in the RISC-V
User-Level ISA document, available from
https://riscv.org/specifications/
Due to revisions of the ISA specification, some deviations
have arisen over time.
Notably, riscv,isa was defined prior to the creation of the
Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i"
implies "zicntr_zicsr_zifencei_zihpm".
While the isa strings in ISA specification are case
insensitive, letters in the riscv,isa string must be all
lowercase.
$ref: /schemas/types.yaml#/definitions/string
pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
deprecated: true
riscv,isa-base:
description:
The base ISA implemented by this hart, as described by the 20191213
version of the unprivileged ISA specification.
enum:
- rv32i
- rv64i
riscv,isa-extensions:
$ref: /schemas/types.yaml#/definitions/string-array
minItems: 1
description: Extensions supported by the hart.
items:
anyOf:
# single letter extensions, in canonical order
- const: i
description: |
The base integer instruction set, as ratified in the 20191213
version of the unprivileged ISA specification.
This does not include Chapter 10, "Counters", which was moved into
the Zicntr and Zihpm extensions after the ratification of the
20191213 version of the unprivileged specification.
- const: m
description:
The standard M extension for integer multiplication and division, as
ratified in the 20191213 version of the unprivileged ISA
specification.
- const: a
description:
The standard A extension for atomic instructions, as ratified in the
20191213 version of the unprivileged ISA specification.
- const: f
description:
The standard F extension for single-precision floating point, as
ratified in the 20191213 version of the unprivileged ISA
specification.
- const: d
description:
The standard D extension for double-precision floating-point, as
ratified in the 20191213 version of the unprivileged ISA
specification.
- const: q
description:
The standard Q extension for quad-precision floating-point, as
ratified in the 20191213 version of the unprivileged ISA
specification.
- const: c
description:
The standard C extension for compressed instructions, as ratified in
the 20191213 version of the unprivileged ISA specification.
- const: v
description:
The standard V extension for vector operations, as ratified
in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f
encoding") of the riscv-v-spec.
- const: h
description:
The standard H extension for hypervisors as ratified in the 20191213
version of the privileged ISA specification.
# multi-letter extensions, sorted alphanumerically
- const: smaia
description: |
The standard Smaia supervisor-level extension for the advanced
interrupt architecture for machine-mode-visible csr and behavioural
changes to interrupts as frozen at commit ccbddab ("Merge pull
request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
- const: ssaia
description: |
The standard Ssaia supervisor-level extension for the advanced
interrupt architecture for supervisor-mode-visible csr and
behavioural changes to interrupts as frozen at commit ccbddab
("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
- const: sscofpmf
description: |
The standard Sscofpmf supervisor-level extension for count overflow
and mode-based filtering as ratified at commit 01d1df0 ("Add ability
to manually trigger workflow. (#2)") of riscv-count-overflow.
- const: sstc
description: |
The standard Sstc supervisor-level extension for time compare as
ratified at commit 3f9ed34 ("Add ability to manually trigger
workflow. (#2)") of riscv-time-compare.
- const: svinval
description:
The standard Svinval supervisor-level extension for fine-grained
address-translation cache invalidation as ratified in the 20191213
version of the privileged ISA specification.
- const: svnapot
description:
The standard Svnapot supervisor-level extensions for napot
translation contiguity as ratified in the 20191213 version of the
privileged ISA specification.
- const: svpbmt
description:
The standard Svpbmt supervisor-level extensions for page-based
memory types as ratified in the 20191213 version of the privileged
ISA specification.
- const: zba
description: |
The standard Zba bit-manipulation extension for address generation
acceleration instructions as ratified at commit 6d33919 ("Merge pull
request #158 from hirooih/clmul-fix-loop-end-condition") of
riscv-bitmanip.
- const: zbb
description: |
The standard Zbb bit-manipulation extension for basic bit-manipulation
as ratified at commit 6d33919 ("Merge pull request #158 from
hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
- const: zbc
description: |
The standard Zbc bit-manipulation extension for carry-less
multiplication as ratified at commit 6d33919 ("Merge pull request
#158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
- const: zbs
description: |
The standard Zbs bit-manipulation extension for single-bit
instructions as ratified at commit 6d33919 ("Merge pull request #158
from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
- const: zicbom
description:
The standard Zicbom extension for base cache management operations as
ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
- const: zicbop
description:
The standard Zicbop extension for cache-block prefetch instructions
as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of
riscv-CMOs.
- const: zicboz
description:
The standard Zicboz extension for cache-block zeroing as ratified
in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
- const: zicntr
description:
The standard Zicntr extension for base counters and timers, as
ratified in the 20191213 version of the unprivileged ISA
specification.
- const: zicsr
description: |
The standard Zicsr extension for control and status register
instructions, as ratified in the 20191213 version of the
unprivileged ISA specification.
This does not include Chapter 10, "Counters", which documents
special case read-only CSRs, that were moved into the Zicntr and
Zihpm extensions after the ratification of the 20191213 version of
the unprivileged specification.
- const: zifencei
description:
The standard Zifencei extension for instruction-fetch fence, as
ratified in the 20191213 version of the unprivileged ISA
specification.
- const: zihintpause
description:
The standard Zihintpause extension for pause hints, as ratified in
commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
- const: zihpm
description:
The standard Zihpm extension for hardware performance counters, as
ratified in the 20191213 version of the unprivileged ISA
specification.
- const: ztso
description:
The standard Ztso extension for total store ordering, as ratified
in commit 2e5236 ("Ztso is now ratified.") of the
riscv-isa-manual.
additionalProperties: true
...

10
Documentation/riscv/acpi.rst Normal file
View file

@ -0,0 +1,10 @@
.. SPDX-License-Identifier: GPL-2.0
==============
ACPI on RISC-V
==============
The ISA string parsing rules for ACPI are defined by `Version ASCIIDOC
Conversion, 12/2022 of the RISC-V specifications, as defined by tag
"riscv-isa-release-1239329-2023-05-23" (commit 1239329
) <https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-1239329-2023-05-23>`_

1
Documentation/riscv/index.rst
View file

@ -5,6 +5,7 @@ RISC-V architecture
.. toctree::
:maxdepth: 1
acpi
boot-image-header
vm-layout
hwprobe

8
Documentation/riscv/vector.rst
View file

@ -130,3 +130,11 @@ processes in form of sysctl knob:
Modifying the system default enablement status does not affect the enablement
status of any existing process of thread that do not make an execve() call.
3. Vector Register State Across System Calls
---------------------------------------------
As indicated by version 1.0 of the V extension [1], vector registers are
clobbered by system calls.
1: https://github.com/riscv/riscv-v-spec/blob/master/calling-convention.adoc

20
arch/riscv/Kconfig
View file

@ -100,11 +100,18 @@ config RISCV
select HAVE_ARCH_THREAD_STRUCT_WHITELIST
select HAVE_ARCH_TRACEHOOK
select HAVE_ARCH_TRANSPARENT_HUGEPAGE if 64BIT && MMU
select HAVE_ARCH_USERFAULTFD_MINOR if 64BIT && USERFAULTFD
select HAVE_ARCH_VMAP_STACK if MMU && 64BIT
select HAVE_ASM_MODVERSIONS
select HAVE_CONTEXT_TRACKING_USER
select HAVE_DEBUG_KMEMLEAK
select HAVE_DMA_CONTIGUOUS if MMU
select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && MMU && (CLANG_SUPPORTS_DYNAMIC_FTRACE || GCC_SUPPORTS_DYNAMIC_FTRACE)
select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
select HAVE_FUNCTION_GRAPH_TRACER
select HAVE_FUNCTION_GRAPH_RETVAL if HAVE_FUNCTION_GRAPH_TRACER
select HAVE_FUNCTION_TRACER if !XIP_KERNEL && !PREEMPTION
select HAVE_EBPF_JIT if MMU
select HAVE_FUNCTION_ARG_ACCESS_API
select HAVE_FUNCTION_ERROR_INJECTION
@ -114,7 +121,8 @@ config RISCV
select HAVE_KPROBES if !XIP_KERNEL
select HAVE_KPROBES_ON_FTRACE if !XIP_KERNEL
select HAVE_KRETPROBES if !XIP_KERNEL
select HAVE_RETHOOK if !XIP_KERNEL
# https://github.com/ClangBuiltLinux/linux/issues/1881
select HAVE_LD_DEAD_CODE_DATA_ELIMINATION if !LD_IS_LLD
select HAVE_MOVE_PMD
select HAVE_MOVE_PUD
select HAVE_PCI
@ -123,6 +131,7 @@ config RISCV
select HAVE_PERF_USER_STACK_DUMP
select HAVE_POSIX_CPU_TIMERS_TASK_WORK
select HAVE_REGS_AND_STACK_ACCESS_API
select HAVE_RETHOOK if !XIP_KERNEL
select HAVE_RSEQ
select HAVE_STACKPROTECTOR
select HAVE_SYSCALL_TRACEPOINTS
@ -148,12 +157,6 @@ config RISCV
select TRACE_IRQFLAGS_SUPPORT
select UACCESS_MEMCPY if !MMU
select ZONE_DMA32 if 64BIT
select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && MMU && (CLANG_SUPPORTS_DYNAMIC_FTRACE || GCC_SUPPORTS_DYNAMIC_FTRACE)
select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
select HAVE_FUNCTION_GRAPH_TRACER
select HAVE_FUNCTION_GRAPH_RETVAL if HAVE_FUNCTION_GRAPH_TRACER
select HAVE_FUNCTION_TRACER if !XIP_KERNEL && !PREEMPTION
config CLANG_SUPPORTS_DYNAMIC_FTRACE
def_bool CC_IS_CLANG
@ -872,6 +875,9 @@ config ARCH_HIBERNATION_POSSIBLE
config ARCH_HIBERNATION_HEADER
def_bool HIBERNATION
config ARCH_SUSPEND_POSSIBLE
def_bool y
endmenu # "Power management options"
menu "CPU Power Management"

7
arch/riscv/errata/thead/errata.c
View file

@ -45,8 +45,11 @@ static bool errata_probe_cmo(unsigned int stage,
if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
return false;
riscv_cbom_block_size = L1_CACHE_BYTES;
riscv_noncoherent_supported();
if (stage == RISCV_ALTERNATIVES_BOOT) {
riscv_cbom_block_size = L1_CACHE_BYTES;
riscv_noncoherent_supported();
}
return true;
}

34
arch/riscv/include/asm/vector.h
View file

@ -33,6 +33,11 @@ static inline void __riscv_v_vstate_clean(struct pt_regs *regs)
regs->status = (regs->status & ~SR_VS) | SR_VS_CLEAN;
}
static inline void __riscv_v_vstate_dirty(struct pt_regs *regs)
{
regs->status = (regs->status & ~SR_VS) | SR_VS_DIRTY;
}
static inline void riscv_v_vstate_off(struct pt_regs *regs)
{
regs->status = (regs->status & ~SR_VS) | SR_VS_OFF;
@ -128,6 +133,34 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_
riscv_v_disable();
}
static inline void __riscv_v_vstate_discard(void)
{
unsigned long vl, vtype_inval = 1UL << (BITS_PER_LONG - 1);
riscv_v_enable();
asm volatile (
".option push\n\t"
".option arch, +v\n\t"
"vsetvli %0, x0, e8, m8, ta, ma\n\t"
"vmv.v.i v0, -1\n\t"
"vmv.v.i v8, -1\n\t"
"vmv.v.i v16, -1\n\t"
"vmv.v.i v24, -1\n\t"
"vsetvl %0, x0, %1\n\t"
".option pop\n\t"
: "=&r" (vl) : "r" (vtype_inval) : "memory");
riscv_v_disable();
}
static inline void riscv_v_vstate_discard(struct pt_regs *regs)
{
if ((regs->status & SR_VS) == SR_VS_OFF)
return;
__riscv_v_vstate_discard();
__riscv_v_vstate_dirty(regs);
}
static inline void riscv_v_vstate_save(struct task_struct *task,
struct pt_regs *regs)
{
@ -173,6 +206,7 @@ static inline bool riscv_v_first_use_handler(struct pt_regs *regs) { return fals
static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return false; }
static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; }
#define riscv_v_vsize (0)
#define riscv_v_vstate_discard(regs) do {} while (0)
#define riscv_v_vstate_save(task, regs) do {} while (0)
#define riscv_v_vstate_restore(task, regs) do {} while (0)
#define __switch_to_vector(__prev, __next) do {} while (0)

4
arch/riscv/include/uapi/asm/sigcontext.h
View file

@ -15,6 +15,8 @@
/* The size of END signal context header. */
#define END_HDR_SIZE 0x0
#ifndef __ASSEMBLY__
struct __sc_riscv_v_state {
struct __riscv_v_ext_state v_state;
} __attribute__((aligned(16)));
@ -33,4 +35,6 @@ struct sigcontext {
};
};
#endif /*!__ASSEMBLY__*/
#endif /* _UAPI_ASM_RISCV_SIGCONTEXT_H */

1
arch/riscv/kernel/smp.c
View file

@ -58,7 +58,6 @@ int riscv_hartid_to_cpuid(unsigned long hartid)
if (cpuid_to_hartid_map(i) == hartid)
return i;
pr_err("Couldn't find cpu id for hartid [%lu]\n", hartid);
return -ENOENT;
}

5
arch/riscv/kernel/smpboot.c
View file

@ -238,10 +238,11 @@ asmlinkage __visible void smp_callin(void)
mmgrab(mm);
current->active_mm = mm;
riscv_ipi_enable();
store_cpu_topology(curr_cpuid);
notify_cpu_starting(curr_cpuid);
riscv_ipi_enable();
numa_add_cpu(curr_cpuid);
set_cpu_online(curr_cpuid, 1);
probe_vendor_features(curr_cpuid);

10
arch/riscv/kernel/traps.c
View file

@ -150,12 +150,18 @@ DO_ERROR_INFO(do_trap_insn_fault,
asmlinkage __visible __trap_section void do_trap_insn_illegal(struct pt_regs *regs)
{
bool handled;
if (user_mode(regs)) {
irqentry_enter_from_user_mode(regs);
local_irq_enable();
if (!riscv_v_first_use_handler(regs))
handled = riscv_v_first_use_handler(regs);
local_irq_disable();
if (!handled)
do_trap_error(regs, SIGILL, ILL_ILLOPC, regs->epc,
"Oops - illegal instruction");
@ -296,6 +302,8 @@ asmlinkage __visible __trap_section void do_trap_ecall_u(struct pt_regs *regs)
regs->epc += 4;
regs->orig_a0 = regs->a0;
riscv_v_vstate_discard(regs);
syscall = syscall_enter_from_user_mode(regs, syscall);
if (syscall < NR_syscalls)

1
arch/riscv/kernel/vdso.c
View file

@ -15,6 +15,7 @@
#include <asm/vdso.h>
#include <linux/time_namespace.h>
#include <vdso/datapage.h>
#include <vdso/vsyscall.h>
enum vvar_pages {
VVAR_DATA_PAGE_OFFSET,

1
arch/riscv/kernel/vector.c
View file

@ -167,6 +167,7 @@ bool riscv_v_first_use_handler(struct pt_regs *regs)
return true;
}
riscv_v_vstate_on(regs);
riscv_v_vstate_restore(current, regs);
return true;
}

6
arch/riscv/kernel/vmlinux-xip.lds.S
View file

@ -98,12 +98,6 @@ SECTIONS
__soc_builtin_dtb_table_end = .;
}
. = ALIGN(8);
.alternative : {
__alt_start = .;
*(.alternative)
__alt_end = .;
}
__init_end = .;
. = ALIGN(16);

6
arch/riscv/kernel/vmlinux.lds.S
View file

@ -85,11 +85,11 @@ SECTIONS
INIT_DATA_SECTION(16)
.init.pi : {
*(.init.pi*)
KEEP(*(.init.pi*))
}
.init.bss : {
*(.init.bss) /* from the EFI stub */
KEEP(*(.init.bss*)) /* from the EFI stub */
}
.exit.data :
{
@ -112,7 +112,7 @@ SECTIONS
. = ALIGN(8);
.alternative : {
__alt_start = .;
*(.alternative)
KEEP(*(.alternative))
__alt_end = .;
}
__init_end = .;

8
arch/riscv/mm/cacheflush.c
View file

@ -104,9 +104,9 @@ EXPORT_SYMBOL_GPL(riscv_cbom_block_size);
unsigned int riscv_cboz_block_size;
EXPORT_SYMBOL_GPL(riscv_cboz_block_size);
static void cbo_get_block_size(struct device_node *node,
const char *name, u32 *block_size,
unsigned long *first_hartid)
static void __init cbo_get_block_size(struct device_node *node,
const char *name, u32 *block_size,
unsigned long *first_hartid)
{
unsigned long hartid;
u32 val;
@ -126,7 +126,7 @@ static void cbo_get_block_size(struct device_node *node,
}
}
void riscv_init_cbo_blocksizes(void)
void __init riscv_init_cbo_blocksizes(void)
{
unsigned long cbom_hartid, cboz_hartid;
u32 cbom_block_size = 0, cboz_block_size = 0;

2
arch/riscv/mm/dma-noncoherent.c
View file

@ -10,7 +10,7 @@
#include <linux/mm.h>
#include <asm/cacheflush.h>
static bool noncoherent_supported;
static bool noncoherent_supported __ro_after_init;
void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
enum dma_data_direction dir)

6
arch/riscv/mm/hugetlbpage.c
View file

@ -73,7 +73,11 @@ pte_t *huge_pte_alloc(struct mm_struct *mm,
}
out:
WARN_ON_ONCE(pte && pte_present(*pte) && !pte_huge(*pte));
if (pte) {
pte_t pteval = ptep_get_lockless(pte);
WARN_ON_ONCE(pte_present(pteval) && !pte_huge(pteval));
}
return pte;
}

4
arch/riscv/mm/init.c
View file

@ -267,7 +267,6 @@ static void __init setup_bootmem(void)
dma_contiguous_reserve(dma32_phys_limit);
if (IS_ENABLED(CONFIG_64BIT))
hugetlb_cma_reserve(PUD_SHIFT - PAGE_SHIFT);
memblock_allow_resize();
}
#ifdef CONFIG_MMU
@ -1370,6 +1369,9 @@ void __init paging_init(void)
{
setup_bootmem();
setup_vm_final();
/* Depend on that Linear Mapping is ready */
memblock_allow_resize();
}
void __init misc_mem_init(void)

2
include/asm-generic/vmlinux.lds.h
View file

@ -688,7 +688,7 @@
/* init and exit section handling */
#define INIT_DATA \
KEEP(*(SORT(___kentry+*))) \
*(.init.data init.data.*) \
*(.init.data .init.data.*) \
MEM_DISCARD(init.data*) \
KERNEL_CTORS() \
MCOUNT_REC() \

1
tools/testing/selftests/riscv/vector/.gitignore vendored
View file

@ -1,2 +1,3 @@
vstate_exec_nolibc
vstate_prctl
v_initval_nolibc

6
tools/testing/selftests/riscv/vector/Makefile
View file

@ -2,7 +2,7 @@
# Copyright (C) 2021 ARM Limited
# Originally tools/testing/arm64/abi/Makefile
TEST_GEN_PROGS := vstate_prctl
TEST_GEN_PROGS := vstate_prctl v_initval_nolibc
TEST_GEN_PROGS_EXTENDED := vstate_exec_nolibc
include ../../lib.mk
@ -13,3 +13,7 @@ $(OUTPUT)/vstate_prctl: vstate_prctl.c ../hwprobe/sys_hwprobe.S
$(OUTPUT)/vstate_exec_nolibc: vstate_exec_nolibc.c
$(CC) -nostdlib -static -include ../../../../include/nolibc/nolibc.h \
-Wall $(CFLAGS) $(LDFLAGS) $^ -o $@ -lgcc
$(OUTPUT)/v_initval_nolibc: v_initval_nolibc.c
$(CC) -nostdlib -static -include ../../../../include/nolibc/nolibc.h \
-Wall $(CFLAGS) $(LDFLAGS) $^ -o $@ -lgcc

68
tools/testing/selftests/riscv/vector/v_initval_nolibc.c Normal file
View file

@ -0,0 +1,68 @@
// SPDX-License-Identifier: GPL-2.0-only
#include "../../kselftest.h"
#define MAX_VSIZE (8192 * 32)
void dump(char *ptr, int size)
{
int i = 0;
for (i = 0; i < size; i++) {
if (i != 0) {
if (i % 16 == 0)
printf("\n");
else if (i % 8 == 0)
printf(" ");
}
printf("%02x ", ptr[i]);
}
printf("\n");
}
int main(void)
{
int i;
unsigned long vl;
char *datap, *tmp;
datap = malloc(MAX_VSIZE);
if (!datap) {
ksft_test_result_fail("fail to allocate memory for size = %lu\n", MAX_VSIZE);
exit(-1);
}
tmp = datap;
asm volatile (
".option push\n\t"
".option arch, +v\n\t"
"vsetvli %0, x0, e8, m8, ta, ma\n\t"
"vse8.v v0, (%2)\n\t"
"add %1, %2, %0\n\t"
"vse8.v v8, (%1)\n\t"
"add %1, %1, %0\n\t"
"vse8.v v16, (%1)\n\t"
"add %1, %1, %0\n\t"
"vse8.v v24, (%1)\n\t"
".option pop\n\t"
: "=&r" (vl), "=r" (tmp) : "r" (datap) : "memory");
ksft_print_msg("vl = %lu\n", vl);
if (datap[0] != 0x00 && datap[0] != 0xff) {
ksft_test_result_fail("v-regesters are not properly initialized\n");
dump(datap, vl * 4);
exit(-1);
}
for (i = 1; i < vl * 4; i++) {
if (datap[i] != datap[0]) {
ksft_test_result_fail("detect stale values on v-regesters\n");
dump(datap, vl * 4);
exit(-2);
}
}
free(datap);
ksft_exit_pass();
return 0;
}