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https://github.com/torvalds/linux
synced 2024-10-25 04:37:40 +00:00
ath5k: simplify MIB counters
Let's keep MIB counter statistics in our own statistics structure and only convert it to ieee80211_low_level_stats when needed by mac80211. Also we don't need to read profile count registers in the MIB interrupt (they don't trigger MIB interrupts). Signed-off-by: Bruno Randolf <br1@einfach.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -1173,8 +1173,7 @@ int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
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bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
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bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
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int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
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int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
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enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask);
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enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask);
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void ath5k_hw_update_mib_counters(struct ath5k_hw *ah,
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void ath5k_hw_update_mib_counters(struct ath5k_hw *ah);
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struct ieee80211_low_level_stats *stats);
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/* EEPROM access functions */
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/* EEPROM access functions */
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int ath5k_eeprom_init(struct ath5k_hw *ah);
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int ath5k_eeprom_init(struct ath5k_hw *ah);
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@ -2114,7 +2114,7 @@ ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
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info->status.rates[ts.ts_final_idx].count++;
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info->status.rates[ts.ts_final_idx].count++;
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if (unlikely(ts.ts_status)) {
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if (unlikely(ts.ts_status)) {
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sc->ll_stats.dot11ACKFailureCount++;
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sc->stats.ack_fail++;
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if (ts.ts_status & AR5K_TXERR_FILT) {
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if (ts.ts_status & AR5K_TXERR_FILT) {
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info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
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info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
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sc->stats.txerr_filt++;
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sc->stats.txerr_filt++;
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@ -2708,11 +2708,7 @@ ath5k_intr(int irq, void *dev_id)
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/* TODO */
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/* TODO */
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}
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}
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if (status & AR5K_INT_MIB) {
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if (status & AR5K_INT_MIB) {
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/*
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ath5k_hw_update_mib_counters(ah);
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* These stats are also used for ANI i think
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* so how about updating them more often ?
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*/
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ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
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}
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}
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if (status & AR5K_INT_GPIO)
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if (status & AR5K_INT_GPIO)
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tasklet_schedule(&sc->rf_kill.toggleq);
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tasklet_schedule(&sc->rf_kill.toggleq);
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@ -3234,12 +3230,14 @@ ath5k_get_stats(struct ieee80211_hw *hw,
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struct ieee80211_low_level_stats *stats)
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struct ieee80211_low_level_stats *stats)
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{
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{
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struct ath5k_softc *sc = hw->priv;
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struct ath5k_softc *sc = hw->priv;
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struct ath5k_hw *ah = sc->ah;
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/* Force update */
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/* Force update */
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ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
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ath5k_hw_update_mib_counters(sc->ah);
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memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
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stats->dot11ACKFailureCount = sc->stats.ack_fail;
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stats->dot11RTSFailureCount = sc->stats.rts_fail;
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stats->dot11RTSSuccessCount = sc->stats.rts_ok;
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stats->dot11FCSErrorCount = sc->stats.fcs_error;
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return 0;
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return 0;
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}
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}
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@ -105,10 +105,13 @@ struct ath5k_rfkill {
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struct tasklet_struct toggleq;
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struct tasklet_struct toggleq;
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};
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};
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/* statistics (only used for debugging now) */
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/* statistics */
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struct ath5k_statistics {
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struct ath5k_statistics {
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/* antenna use */
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unsigned int antenna_rx[5]; /* frames count per antenna RX */
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unsigned int antenna_rx[5]; /* frames count per antenna RX */
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unsigned int antenna_tx[5]; /* frames count per antenna TX */
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unsigned int antenna_tx[5]; /* frames count per antenna TX */
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/* frame errors */
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unsigned int rx_all_count; /* all RX frames, including errors */
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unsigned int rx_all_count; /* all RX frames, including errors */
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unsigned int tx_all_count; /* all TX frames, including errors */
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unsigned int tx_all_count; /* all TX frames, including errors */
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unsigned int rxerr_crc;
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unsigned int rxerr_crc;
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@ -121,6 +124,13 @@ struct ath5k_statistics {
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unsigned int txerr_retry;
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unsigned int txerr_retry;
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unsigned int txerr_fifo;
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unsigned int txerr_fifo;
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unsigned int txerr_filt;
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unsigned int txerr_filt;
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/* MIB counters */
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unsigned int ack_fail;
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unsigned int rts_fail;
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unsigned int rts_ok;
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unsigned int fcs_error;
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unsigned int beacons;
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};
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};
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#if CHAN_DEBUG
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#if CHAN_DEBUG
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@ -135,7 +145,6 @@ struct ath5k_softc {
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struct pci_dev *pdev; /* for dma mapping */
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struct pci_dev *pdev; /* for dma mapping */
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void __iomem *iobase; /* address of the device */
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void __iomem *iobase; /* address of the device */
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struct mutex lock; /* dev-level lock */
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struct mutex lock; /* dev-level lock */
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struct ieee80211_low_level_stats ll_stats;
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struct ieee80211_hw *hw; /* IEEE 802.11 common */
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struct ieee80211_hw *hw; /* IEEE 802.11 common */
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struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
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struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
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struct ieee80211_channel channels[ATH_CHAN_MAX];
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struct ieee80211_channel channels[ATH_CHAN_MAX];
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@ -113,39 +113,26 @@ int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
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}
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}
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/**
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/**
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* ath5k_hw_update - Update mib counters (mac layer statistics)
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* ath5k_hw_update - Update MIB counters (mac layer statistics)
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*
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*
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* @ah: The &struct ath5k_hw
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* @ah: The &struct ath5k_hw
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* @stats: The &struct ieee80211_low_level_stats we use to track
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* statistics on the driver
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*
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*
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* Reads MIB counters from PCU and updates sw statistics. Must be
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* Reads MIB counters from PCU and updates sw statistics. Is called after a
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* called after a MIB interrupt.
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* MIB interrupt, because one of these counters might have reached their maximum
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* and triggered the MIB interrupt, to let us read and clear the counter.
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*
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* Is called in interrupt context!
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*/
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*/
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void ath5k_hw_update_mib_counters(struct ath5k_hw *ah,
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void ath5k_hw_update_mib_counters(struct ath5k_hw *ah)
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struct ieee80211_low_level_stats *stats)
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{
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{
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ATH5K_TRACE(ah->ah_sc);
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struct ath5k_statistics *stats = &ah->ah_sc->stats;
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/* Read-And-Clear */
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/* Read-And-Clear */
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stats->dot11ACKFailureCount += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
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stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
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stats->dot11RTSFailureCount += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
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stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
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stats->dot11RTSSuccessCount += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
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stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
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stats->dot11FCSErrorCount += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
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stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
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stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
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/* XXX: Should we use this to track beacon count ?
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* -we read it anyway to clear the register */
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ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
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/* Reset profile count registers on 5212*/
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if (ah->ah_version == AR5K_AR5212) {
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ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_TX);
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ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RX);
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ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RXCLR);
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ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_CYCLE);
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}
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/* TODO: Handle ANI stats */
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}
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}
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/**
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/**
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