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ASoC: rsnd: adg: Fix BRG typos
"BRG" stands for "Baud Rate Generator", but is frequently misspelled as "RBG". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/ac6365c17861d71fbc89d823089db4aafdb763ed.1676470202.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -39,10 +39,10 @@ struct rsnd_adg {
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int clkin_size;
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int clkout_size;
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u32 ckr;
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u32 rbga;
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u32 rbgb;
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u32 brga;
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u32 brgb;
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int rbg_rate[ADG_HZ_SIZE]; /* RBGA / RBGB */
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int brg_rate[ADG_HZ_SIZE]; /* BRGA / BRGB */
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};
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#define for_each_rsnd_clkin(pos, adg, i) \
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@ -75,7 +75,7 @@ static const char * const clkout_name_gen2[] = {
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[CLKOUT3] = "audio_clkout3",
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};
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static u32 rsnd_adg_calculate_rbgx(unsigned long div)
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static u32 rsnd_adg_calculate_brgx(unsigned long div)
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{
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int i;
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@ -131,8 +131,8 @@ static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
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adg->clkin_rate[CLKA], /* 0000: CLKA */
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adg->clkin_rate[CLKB], /* 0001: CLKB */
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adg->clkin_rate[CLKC], /* 0010: CLKC */
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adg->rbg_rate[ADG_HZ_441], /* 0011: RBGA */
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adg->rbg_rate[ADG_HZ_48], /* 0100: RBGB */
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adg->brg_rate[ADG_HZ_441], /* 0011: BRGA */
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adg->brg_rate[ADG_HZ_48], /* 0100: BRGB */
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};
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min = ~0;
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@ -323,10 +323,10 @@ int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate)
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/*
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* find divided clock from BRGA/BRGB
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*/
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if (rate == adg->rbg_rate[ADG_HZ_441])
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if (rate == adg->brg_rate[ADG_HZ_441])
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return 0x10;
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if (rate == adg->rbg_rate[ADG_HZ_48])
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if (rate == adg->brg_rate[ADG_HZ_48])
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return 0x20;
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return -EIO;
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@ -358,13 +358,13 @@ int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
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ckr = 0x80000000; /* BRGB output = 48kHz */
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rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr);
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rsnd_mod_write(adg_mod, BRRA, adg->rbga);
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rsnd_mod_write(adg_mod, BRRB, adg->rbgb);
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rsnd_mod_write(adg_mod, BRRA, adg->brga);
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rsnd_mod_write(adg_mod, BRRB, adg->brgb);
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dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n",
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(ckr) ? 'B' : 'A',
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(ckr) ? adg->rbg_rate[ADG_HZ_48] :
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adg->rbg_rate[ADG_HZ_441]);
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(ckr) ? adg->brg_rate[ADG_HZ_48] :
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adg->brg_rate[ADG_HZ_441]);
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return 0;
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}
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@ -484,7 +484,7 @@ static int rsnd_adg_get_clkout(struct rsnd_priv *priv)
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struct device *dev = rsnd_priv_to_dev(priv);
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struct device_node *np = dev->of_node;
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struct property *prop;
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u32 ckr, rbgx, rbga, rbgb;
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u32 ckr, brgx, brga, brgb;
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u32 rate, div;
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u32 req_rate[ADG_HZ_SIZE] = {};
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uint32_t count = 0;
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@ -501,8 +501,8 @@ static int rsnd_adg_get_clkout(struct rsnd_priv *priv)
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};
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ckr = 0;
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rbga = 2; /* default 1/6 */
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rbgb = 2; /* default 1/6 */
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brga = 2; /* default 1/6 */
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brgb = 2; /* default 1/6 */
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/*
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* ADG supports BRRA/BRRB output only
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@ -543,30 +543,30 @@ static int rsnd_adg_get_clkout(struct rsnd_priv *priv)
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if (0 == rate) /* not used */
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continue;
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/* RBGA */
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if (!adg->rbg_rate[ADG_HZ_441] && (0 == rate % 44100)) {
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/* BRGA */
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if (!adg->brg_rate[ADG_HZ_441] && (0 == rate % 44100)) {
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div = 6;
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if (req_Hz[ADG_HZ_441])
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div = rate / req_Hz[ADG_HZ_441];
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rbgx = rsnd_adg_calculate_rbgx(div);
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if (BRRx_MASK(rbgx) == rbgx) {
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rbga = rbgx;
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adg->rbg_rate[ADG_HZ_441] = rate / div;
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brgx = rsnd_adg_calculate_brgx(div);
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if (BRRx_MASK(brgx) == brgx) {
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brga = brgx;
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adg->brg_rate[ADG_HZ_441] = rate / div;
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ckr |= brg_table[i] << 20;
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if (req_Hz[ADG_HZ_441])
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parent_clk_name = __clk_get_name(clk);
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}
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}
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/* RBGB */
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if (!adg->rbg_rate[ADG_HZ_48] && (0 == rate % 48000)) {
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/* BRGB */
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if (!adg->brg_rate[ADG_HZ_48] && (0 == rate % 48000)) {
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div = 6;
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if (req_Hz[ADG_HZ_48])
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div = rate / req_Hz[ADG_HZ_48];
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rbgx = rsnd_adg_calculate_rbgx(div);
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if (BRRx_MASK(rbgx) == rbgx) {
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rbgb = rbgx;
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adg->rbg_rate[ADG_HZ_48] = rate / div;
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brgx = rsnd_adg_calculate_brgx(div);
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if (BRRx_MASK(brgx) == brgx) {
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brgb = brgx;
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adg->brg_rate[ADG_HZ_48] = rate / div;
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ckr |= brg_table[i] << 16;
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if (req_Hz[ADG_HZ_48])
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parent_clk_name = __clk_get_name(clk);
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@ -620,8 +620,8 @@ static int rsnd_adg_get_clkout(struct rsnd_priv *priv)
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rsnd_adg_get_clkout_end:
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adg->ckr = ckr;
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adg->rbga = rbga;
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adg->rbgb = rbgb;
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adg->brga = brga;
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adg->brgb = brgb;
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return 0;
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@ -663,9 +663,9 @@ void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct seq_file *m)
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__clk_get_name(clk), clk, clk_get_rate(clk));
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dbg_msg(dev, m, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
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adg->ckr, adg->rbga, adg->rbgb);
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dbg_msg(dev, m, "BRGA (for 44100 base) = %d\n", adg->rbg_rate[ADG_HZ_441]);
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dbg_msg(dev, m, "BRGB (for 48000 base) = %d\n", adg->rbg_rate[ADG_HZ_48]);
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adg->ckr, adg->brga, adg->brgb);
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dbg_msg(dev, m, "BRGA (for 44100 base) = %d\n", adg->brg_rate[ADG_HZ_441]);
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dbg_msg(dev, m, "BRGB (for 48000 base) = %d\n", adg->brg_rate[ADG_HZ_48]);
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/*
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* Actual CLKOUT will be exchanged in rsnd_adg_ssi_clk_try_start()
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