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PCI: rockchip: Provide captured slot power limit and scale
If vpcie3v3 is available, we could provide these information via RC's configure register to make EP able to know the power limit. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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@ -135,6 +135,10 @@
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#define PCIE_RC_CONFIG_VENDOR (PCIE_RC_CONFIG_BASE + 0x00)
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#define PCIE_RC_CONFIG_VENDOR (PCIE_RC_CONFIG_BASE + 0x00)
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#define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
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#define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
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#define PCIE_RC_CONFIG_SCC_SHIFT 16
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#define PCIE_RC_CONFIG_SCC_SHIFT 16
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#define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4)
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#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
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#define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff
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#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
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#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
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#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
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#define PCIE_RC_CONFIG_LCS_RETRAIN_LINK BIT(5)
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#define PCIE_RC_CONFIG_LCS_RETRAIN_LINK BIT(5)
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#define PCIE_RC_CONFIG_LCS_LBMIE BIT(10)
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#define PCIE_RC_CONFIG_LCS_LBMIE BIT(10)
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@ -398,6 +402,40 @@ static struct pci_ops rockchip_pcie_ops = {
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.write = rockchip_pcie_wr_conf,
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.write = rockchip_pcie_wr_conf,
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};
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};
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static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip)
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{
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u32 status, curr, scale, power;
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if (IS_ERR(rockchip->vpcie3v3))
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return;
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/*
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* Set RC's captured slot power limit and scale if
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* vpcie3v3 available. The default values are both zero
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* which means the software should set these two according
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* to the actual power supply.
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*/
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curr = regulator_get_current_limit(rockchip->vpcie3v3);
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if (curr > 0) {
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scale = 3; /* 0.001x */
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curr = curr / 1000; /* convert to mA */
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power = (curr * 3300) / 1000; /* milliwatt */
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while (power > PCIE_RC_CONFIG_DCR_CSPL_LIMIT) {
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if (!scale) {
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dev_warn(rockchip->dev, "invalid power supply\n");
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return;
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}
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scale--;
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power = power / 10;
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}
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status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCR);
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status |= (power << PCIE_RC_CONFIG_DCR_CSPL_SHIFT) |
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(scale << PCIE_RC_CONFIG_DCR_CPLS_SHIFT);
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rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR);
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}
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}
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/**
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/**
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* rockchip_pcie_init_port - Initialize hardware
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* rockchip_pcie_init_port - Initialize hardware
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* @rockchip: PCIe port information
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* @rockchip: PCIe port information
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@ -537,6 +575,8 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
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(PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
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(PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
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rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1);
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rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1);
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rockchip_pcie_set_power_limit(rockchip);
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/* Enable Gen1 training */
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/* Enable Gen1 training */
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rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
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rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
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PCIE_CLIENT_CONFIG);
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PCIE_CLIENT_CONFIG);
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