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https://github.com/torvalds/linux
synced 2024-07-24 03:59:21 +00:00
MIPS: Convert R4600_V2_HIT_CACHEOP into a config option
Use a new config option to enable R4600 V2 cacheop hit workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
parent
5e5b652712
commit
44def3426e
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@ -640,6 +640,7 @@ config SGI_IP22
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_SUPPORTS_BIG_ENDIAN
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select WAR_R4600_V1_INDEX_ICACHEOP
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select WAR_R4600_V1_INDEX_ICACHEOP
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select WAR_R4600_V1_HIT_CACHEOP
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select WAR_R4600_V1_HIT_CACHEOP
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select WAR_R4600_V2_HIT_CACHEOP
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select MIPS_L1_CACHE_SHIFT_7
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select MIPS_L1_CACHE_SHIFT_7
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help
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help
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This are the SGI Indy, Challenge S and Indigo2, as well as certain
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This are the SGI Indy, Challenge S and Indigo2, as well as certain
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@ -877,6 +878,7 @@ config SNI_RM
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_SUPPORTS_HIGHMEM
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select SYS_SUPPORTS_HIGHMEM
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select WAR_R4600_V2_HIT_CACHEOP
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help
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help
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The SNI RM200/300/400 are MIPS-based machines manufactured by
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The SNI RM200/300/400 are MIPS-based machines manufactured by
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Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
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Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
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@ -2643,6 +2645,18 @@ config WAR_R4600_V1_INDEX_ICACHEOP
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config WAR_R4600_V1_HIT_CACHEOP
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config WAR_R4600_V1_HIT_CACHEOP
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bool
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bool
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# Writeback and invalidate the primary cache dcache before DMA.
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#
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# R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
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# Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
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# operate correctly if the internal data cache refill buffer is empty. These
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# CACHE instructions should be separated from any potential data cache miss
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# by a load instruction to an uncached address to empty the response buffer."
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# (Revision 2.0 device errata from IDT available on https://www.idt.com/
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# in .pdf format.)
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config WAR_R4600_V2_HIT_CACHEOP
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bool
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#
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#
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# - Highmem only makes sense for the 32-bit kernel.
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# - Highmem only makes sense for the 32-bit kernel.
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# - The current highmem code will only work properly on physically indexed
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# - The current highmem code will only work properly on physically indexed
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@ -9,7 +9,6 @@
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#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
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#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
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#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
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#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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@ -8,7 +8,6 @@
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#ifndef __ASM_MACH_GENERIC_WAR_H
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#ifndef __ASM_MACH_GENERIC_WAR_H
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#define __ASM_MACH_GENERIC_WAR_H
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#define __ASM_MACH_GENERIC_WAR_H
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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@ -8,11 +8,6 @@
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#ifndef __ASM_MIPS_MACH_IP22_WAR_H
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#ifndef __ASM_MIPS_MACH_IP22_WAR_H
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#define __ASM_MIPS_MACH_IP22_WAR_H
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#define __ASM_MIPS_MACH_IP22_WAR_H
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/*
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* R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
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*/
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#define R4600_V2_HIT_CACHEOP_WAR 1
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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@ -8,7 +8,6 @@
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#ifndef __ASM_MIPS_MACH_IP27_WAR_H
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#ifndef __ASM_MIPS_MACH_IP27_WAR_H
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#define __ASM_MIPS_MACH_IP27_WAR_H
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#define __ASM_MIPS_MACH_IP27_WAR_H
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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@ -8,7 +8,6 @@
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#ifndef __ASM_MIPS_MACH_IP28_WAR_H
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#ifndef __ASM_MIPS_MACH_IP28_WAR_H
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#define __ASM_MIPS_MACH_IP28_WAR_H
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#define __ASM_MIPS_MACH_IP28_WAR_H
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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@ -5,7 +5,6 @@
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#ifndef __ASM_MIPS_MACH_IP30_WAR_H
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#ifndef __ASM_MIPS_MACH_IP30_WAR_H
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#define __ASM_MIPS_MACH_IP30_WAR_H
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#define __ASM_MIPS_MACH_IP30_WAR_H
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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@ -8,7 +8,6 @@
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#ifndef __ASM_MIPS_MACH_IP32_WAR_H
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#ifndef __ASM_MIPS_MACH_IP32_WAR_H
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#define __ASM_MIPS_MACH_IP32_WAR_H
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#define __ASM_MIPS_MACH_IP32_WAR_H
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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@ -8,7 +8,6 @@
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#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
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#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
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#define __ASM_MIPS_MACH_MIPS_WAR_H
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#define __ASM_MIPS_MACH_MIPS_WAR_H
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 1
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#define MIPS4K_ICACHE_REFILL_WAR 1
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@ -8,7 +8,6 @@
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#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
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#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
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#define __ASM_MIPS_MACH_MIPS_WAR_H
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#define __ASM_MIPS_MACH_MIPS_WAR_H
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 1
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#define MIPS4K_ICACHE_REFILL_WAR 1
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@ -8,11 +8,6 @@
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#ifndef __ASM_MIPS_MACH_RM_WAR_H
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#ifndef __ASM_MIPS_MACH_RM_WAR_H
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#define __ASM_MIPS_MACH_RM_WAR_H
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#define __ASM_MIPS_MACH_RM_WAR_H
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/*
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* The RM200C seems to have been shipped only with V2.0 R4600s
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*/
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#define R4600_V2_HIT_CACHEOP_WAR 1
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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@ -8,8 +8,6 @@
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#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
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#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
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#define __ASM_MIPS_MACH_SIBYTE_WAR_H
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#define __ASM_MIPS_MACH_SIBYTE_WAR_H
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#if defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
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#if defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLY__
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@ -8,7 +8,6 @@
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#ifndef __ASM_MIPS_MACH_TX49XX_WAR_H
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#ifndef __ASM_MIPS_MACH_TX49XX_WAR_H
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#define __ASM_MIPS_MACH_TX49XX_WAR_H
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#define __ASM_MIPS_MACH_TX49XX_WAR_H
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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@ -72,21 +72,6 @@
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#define DADDI_WAR 0
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#define DADDI_WAR 0
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#endif
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#endif
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/*
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* Writeback and invalidate the primary cache dcache before DMA.
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*
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* R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
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* Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
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* operate correctly if the internal data cache refill buffer is empty. These
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* CACHE instructions should be separated from any potential data cache miss
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* by a load instruction to an uncached address to empty the response buffer."
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* (Revision 2.0 device errata from IDT available on https://www.idt.com/
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* in .pdf format.)
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*/
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#ifndef R4600_V2_HIT_CACHEOP_WAR
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#error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform
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#endif
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/*
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/*
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* Workaround for the Sibyte M3 errata the text of which can be found at
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* Workaround for the Sibyte M3 errata the text of which can be found at
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*
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*
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@ -130,7 +130,8 @@ struct bcache_ops *bcops = &no_sc_ops;
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#define R4600_HIT_CACHEOP_WAR_IMPL \
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#define R4600_HIT_CACHEOP_WAR_IMPL \
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do { \
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do { \
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if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
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if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) && \
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cpu_is_r4600_v2_x()) \
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*(volatile unsigned long *)CKSEG1; \
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*(volatile unsigned long *)CKSEG1; \
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if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP)) \
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if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP)) \
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__asm__ __volatile__("nop;nop;nop;nop"); \
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__asm__ __volatile__("nop;nop;nop;nop"); \
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@ -258,7 +258,8 @@ static inline void build_clear_pref(u32 **buf, int off)
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uasm_i_nop(buf);
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uasm_i_nop(buf);
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}
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}
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if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
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if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) &&
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cpu_is_r4600_v2_x())
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uasm_i_lw(buf, ZERO, ZERO, AT);
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uasm_i_lw(buf, ZERO, ZERO, AT);
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uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
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uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
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@ -303,7 +304,7 @@ void build_clear_page(void)
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else
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else
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uasm_i_ori(&buf, A2, A0, off);
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uasm_i_ori(&buf, A2, A0, off);
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if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
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if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) && cpu_is_r4600_v2_x())
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uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));
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uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));
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off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size)
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off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size)
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@ -411,7 +412,8 @@ static inline void build_copy_store_pref(u32 **buf, int off)
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uasm_i_nop(buf);
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uasm_i_nop(buf);
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}
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}
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if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
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if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) &&
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cpu_is_r4600_v2_x())
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uasm_i_lw(buf, ZERO, ZERO, AT);
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uasm_i_lw(buf, ZERO, ZERO, AT);
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uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
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uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
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@ -455,7 +457,7 @@ void build_copy_page(void)
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else
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else
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uasm_i_ori(&buf, A2, A0, off);
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uasm_i_ori(&buf, A2, A0, off);
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if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
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if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) && cpu_is_r4600_v2_x())
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uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));
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uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));
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off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) *
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off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) *
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