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MIPS: Convert R4600_V2_HIT_CACHEOP into a config option

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Use a new config option to enable R4600 V2 cacheop hit workaround
and remove define from different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Thomas Bogendoerfer 2020-08-24 18:32:45 +02:00
parent 5e5b652712
commit 44def3426e
16 changed files with 22 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
arch/mips/Kconfig
View File

@ -640,6 +640,7 @@ config SGI_IP22
select SYS_SUPPORTS_BIG_ENDIAN
select WAR_R4600_V1_INDEX_ICACHEOP
select WAR_R4600_V1_HIT_CACHEOP
select WAR_R4600_V2_HIT_CACHEOP
select MIPS_L1_CACHE_SHIFT_7
help
This are the SGI Indy, Challenge S and Indigo2, as well as certain
@ -877,6 +878,7 @@ config SNI_RM
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
select WAR_R4600_V2_HIT_CACHEOP
help
The SNI RM200/300/400 are MIPS-based machines manufactured by
Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
@ -2643,6 +2645,18 @@ config WAR_R4600_V1_INDEX_ICACHEOP
config WAR_R4600_V1_HIT_CACHEOP
bool
# Writeback and invalidate the primary cache dcache before DMA.
#
# R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
# Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
# operate correctly if the internal data cache refill buffer is empty. These
# CACHE instructions should be separated from any potential data cache miss
# by a load instruction to an uncached address to empty the response buffer."
# (Revision 2.0 device errata from IDT available on https://www.idt.com/
# in .pdf format.)
config WAR_R4600_V2_HIT_CACHEOP
bool
#
# - Highmem only makes sense for the 32-bit kernel.
# - The current highmem code will only work properly on physically indexed

1
arch/mips/include/asm/mach-cavium-octeon/war.h
View File

@ -9,7 +9,6 @@
#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0

1
arch/mips/include/asm/mach-generic/war.h
View File

@ -8,7 +8,6 @@
#ifndef __ASM_MACH_GENERIC_WAR_H
#define __ASM_MACH_GENERIC_WAR_H
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0

5
arch/mips/include/asm/mach-ip22/war.h
View File

@ -8,11 +8,6 @@
#ifndef __ASM_MIPS_MACH_IP22_WAR_H
#define __ASM_MIPS_MACH_IP22_WAR_H
/*
* R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
*/
#define R4600_V2_HIT_CACHEOP_WAR 1
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0

1
arch/mips/include/asm/mach-ip27/war.h
View File

@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_IP27_WAR_H
#define __ASM_MIPS_MACH_IP27_WAR_H
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0

1
arch/mips/include/asm/mach-ip28/war.h
View File

@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_IP28_WAR_H
#define __ASM_MIPS_MACH_IP28_WAR_H
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0

1
arch/mips/include/asm/mach-ip30/war.h
View File

@ -5,7 +5,6 @@
#ifndef __ASM_MIPS_MACH_IP30_WAR_H
#define __ASM_MIPS_MACH_IP30_WAR_H
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0

1
arch/mips/include/asm/mach-ip32/war.h
View File

@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_IP32_WAR_H
#define __ASM_MIPS_MACH_IP32_WAR_H
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0

1
arch/mips/include/asm/mach-malta/war.h
View File

@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
#define __ASM_MIPS_MACH_MIPS_WAR_H
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 1

1
arch/mips/include/asm/mach-rc32434/war.h
View File

@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
#define __ASM_MIPS_MACH_MIPS_WAR_H
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 1

5
arch/mips/include/asm/mach-rm/war.h
View File

@ -8,11 +8,6 @@
#ifndef __ASM_MIPS_MACH_RM_WAR_H
#define __ASM_MIPS_MACH_RM_WAR_H
/*
* The RM200C seems to have been shipped only with V2.0 R4600s
*/
#define R4600_V2_HIT_CACHEOP_WAR 1
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0

2
arch/mips/include/asm/mach-sibyte/war.h
View File

@ -8,8 +8,6 @@
#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
#define __ASM_MIPS_MACH_SIBYTE_WAR_H
#define R4600_V2_HIT_CACHEOP_WAR 0
#if defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
#ifndef __ASSEMBLY__

1
arch/mips/include/asm/mach-tx49xx/war.h
View File

@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_TX49XX_WAR_H
#define __ASM_MIPS_MACH_TX49XX_WAR_H
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0

15
arch/mips/include/asm/war.h
View File

@ -72,21 +72,6 @@
#define DADDI_WAR 0
#endif
/*
* Writeback and invalidate the primary cache dcache before DMA.
*
* R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
* Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
* operate correctly if the internal data cache refill buffer is empty. These
* CACHE instructions should be separated from any potential data cache miss
* by a load instruction to an uncached address to empty the response buffer."
* (Revision 2.0 device errata from IDT available on https://www.idt.com/
* in .pdf format.)
*/
#ifndef R4600_V2_HIT_CACHEOP_WAR
#error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform
#endif
/*
* Workaround for the Sibyte M3 errata the text of which can be found at
*

3
arch/mips/mm/c-r4k.c
View File

@ -130,7 +130,8 @@ struct bcache_ops *bcops = &no_sc_ops;
#define R4600_HIT_CACHEOP_WAR_IMPL \
do { \
if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) && \
cpu_is_r4600_v2_x()) \
*(volatile unsigned long *)CKSEG1; \
if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP)) \
__asm__ __volatile__("nop;nop;nop;nop"); \

10
arch/mips/mm/page.c
View File

@ -258,7 +258,8 @@ static inline void build_clear_pref(u32 **buf, int off)
uasm_i_nop(buf);
}
if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) &&
cpu_is_r4600_v2_x())
uasm_i_lw(buf, ZERO, ZERO, AT);
uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
@ -303,7 +304,7 @@ void build_clear_page(void)
else
uasm_i_ori(&buf, A2, A0, off);
if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) && cpu_is_r4600_v2_x())
uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));
off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size)
@ -411,7 +412,8 @@ static inline void build_copy_store_pref(u32 **buf, int off)
uasm_i_nop(buf);
}
if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) &&
cpu_is_r4600_v2_x())
uasm_i_lw(buf, ZERO, ZERO, AT);
uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
@ -455,7 +457,7 @@ void build_copy_page(void)
else
uasm_i_ori(&buf, A2, A0, off);
if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) && cpu_is_r4600_v2_x())
uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));
off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) *