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iio: dac: ad5686: Fix alignment for DMA safety

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____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Update the comment to include 'may'.

Fixes: 0357e488b8 ("iio:dac:ad5686: Refactor the driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-50-jic23@kernel.org
This commit is contained in:
Jonathan Cameron 2022-05-08 18:56:29 +01:00
parent 4a4a79c06c
commit 444e38927d
1 changed files with 4 additions and 2 deletions
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6
drivers/iio/dac/ad5686.h
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@ -13,6 +13,8 @@
#include <linux/mutex.h>
#include <linux/kernel.h>
#include <linux/iio/iio.h>
#define AD5310_CMD(x) ((x) << 12)
#define AD5683_DATA(x) ((x) << 4)
@ -137,7 +139,7 @@ struct ad5686_state {
struct mutex lock;
/*
* DMA (thus cache coherency maintenance) requires the
* DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
*/
@ -145,7 +147,7 @@ struct ad5686_state {
__be32 d32;
__be16 d16;
u8 d8[4];
} data[3] ____cacheline_aligned;
} data[3] __aligned(IIO_DMA_MINALIGN);
};