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drm/xe/hwmon: Expose power1_max_interval
Expose power1_max_interval, that is the tau corresponding to PL1, as a custom hwmon attribute. Some bit manipulation is needed because of the format of PKG_PWR_LIM_1_TIME in PACKAGE_RAPL_LIMIT register (1.x * power(2,y)) v2: Get rpm wake ref while accessing power1_max_interval v3: %s/hwmon/xe_hwmon/ v4: - As power1_max_interval is rw attr take lock in read function as well - Refine comment about val to fix point conversion (Andi) - Update kernel version and date in doc v5: Fix review comments (Anshuman) Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231030115618.1382200-4-badal.nilawar@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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@ -59,3 +59,12 @@ Contact: intel-xe@lists.freedesktop.org
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Description: RO. Energy input of device in microjoules.
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Only supported for particular Intel xe graphics platforms.
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What: /sys/devices/.../hwmon/hwmon<i>/power1_max_interval
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Date: October 2023
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KernelVersion: 6.6
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Contact: intel-xe@lists.freedesktop.org
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Description: RW. Sustained power limit interval (Tau in PL1/Tau) in
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milliseconds over which sustained power is averaged.
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Only supported for particular Intel xe graphics platforms.
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@ -22,15 +22,23 @@
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#define PKG_TDP GENMASK_ULL(14, 0)
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#define PKG_MIN_PWR GENMASK_ULL(30, 16)
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#define PKG_MAX_PWR GENMASK_ULL(46, 32)
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#define PKG_MAX_WIN GENMASK_ULL(54, 48)
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#define PKG_MAX_WIN_X GENMASK_ULL(54, 53)
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#define PKG_MAX_WIN_Y GENMASK_ULL(52, 48)
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#define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
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#define PKG_PWR_UNIT REG_GENMASK(3, 0)
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#define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
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#define PKG_TIME_UNIT REG_GENMASK(19, 16)
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#define PCU_CR_PACKAGE_ENERGY_STATUS XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)
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#define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
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#define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
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#define PKG_PWR_LIM_1_EN REG_BIT(15)
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#define PKG_PWR_LIM_1_TIME REG_GENMASK(23, 17)
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#define PKG_PWR_LIM_1_TIME_X REG_GENMASK(23, 22)
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#define PKG_PWR_LIM_1_TIME_Y REG_GENMASK(21, 17)
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#endif /* _XE_MCHBAR_REGS_H_ */
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@ -38,6 +38,7 @@ enum xe_hwmon_reg_operation {
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#define SF_CURR 1000 /* milliamperes */
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#define SF_VOLTAGE 1000 /* millivolts */
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#define SF_ENERGY 1000000 /* microjoules */
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#define SF_TIME 1000 /* milliseconds */
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/**
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* struct xe_hwmon_energy_info - to accumulate energy
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@ -63,6 +64,8 @@ struct xe_hwmon {
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int scl_shift_power;
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/** @scl_shift_energy: pkg energy unit */
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int scl_shift_energy;
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/** @scl_shift_time: pkg time unit */
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int scl_shift_time;
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/** @ei: Energy info for energy1_input */
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struct xe_hwmon_energy_info ei;
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};
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@ -253,6 +256,152 @@ xe_hwmon_energy_get(struct xe_hwmon *hwmon, long *energy)
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hwmon->scl_shift_energy);
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}
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static ssize_t
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xe_hwmon_power1_max_interval_show(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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struct xe_hwmon *hwmon = dev_get_drvdata(dev);
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u32 x, y, x_w = 2; /* 2 bits */
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u64 r, tau4, out;
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xe_device_mem_access_get(gt_to_xe(hwmon->gt));
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mutex_lock(&hwmon->hwmon_lock);
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xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT,
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REG_READ32, &r, 0, 0);
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mutex_unlock(&hwmon->hwmon_lock);
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xe_device_mem_access_put(gt_to_xe(hwmon->gt));
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x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r);
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y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r);
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/*
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* tau = 1.x * power(2,y), x = bits(23:22), y = bits(21:17)
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* = (4 | x) << (y - 2)
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*
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* Here (y - 2) ensures a 1.x fixed point representation of 1.x
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* As x is 2 bits so 1.x can be 1.0, 1.25, 1.50, 1.75
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*
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* As y can be < 2, we compute tau4 = (4 | x) << y
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* and then add 2 when doing the final right shift to account for units
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*/
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tau4 = ((1 << x_w) | x) << y;
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/* val in hwmon interface units (millisec) */
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out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
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return sysfs_emit(buf, "%llu\n", out);
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}
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static ssize_t
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xe_hwmon_power1_max_interval_store(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct xe_hwmon *hwmon = dev_get_drvdata(dev);
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u32 x, y, rxy, x_w = 2; /* 2 bits */
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u64 tau4, r, max_win;
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unsigned long val;
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int ret;
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ret = kstrtoul(buf, 0, &val);
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if (ret)
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return ret;
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/*
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* Max HW supported tau in '1.x * power(2,y)' format, x = 0, y = 0x12.
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* The hwmon->scl_shift_time default of 0xa results in a max tau of 256 seconds.
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*
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* The ideal scenario is for PKG_MAX_WIN to be read from the PKG_PWR_SKU register.
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* However, it is observed that existing discrete GPUs does not provide correct
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* PKG_MAX_WIN value, therefore a using default constant value. For future discrete GPUs
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* this may get resolved, in which case PKG_MAX_WIN should be obtained from PKG_PWR_SKU.
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*/
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#define PKG_MAX_WIN_DEFAULT 0x12ull
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/*
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* val must be < max in hwmon interface units. The steps below are
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* explained in xe_hwmon_power1_max_interval_show()
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*/
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r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT);
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x = REG_FIELD_GET(PKG_MAX_WIN_X, r);
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y = REG_FIELD_GET(PKG_MAX_WIN_Y, r);
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tau4 = ((1 << x_w) | x) << y;
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max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
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if (val > max_win)
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return -EINVAL;
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/* val in hw units */
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val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME);
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/*
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* Convert val to 1.x * power(2,y)
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* y = ilog2(val)
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* x = (val - (1 << y)) >> (y - 2)
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*/
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if (!val) {
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y = 0;
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x = 0;
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} else {
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y = ilog2(val);
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x = (val - (1ul << y)) << x_w >> y;
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}
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rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) | REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y);
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xe_device_mem_access_get(gt_to_xe(hwmon->gt));
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mutex_lock(&hwmon->hwmon_lock);
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xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW32, (u64 *)&r,
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PKG_PWR_LIM_1_TIME, rxy);
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mutex_unlock(&hwmon->hwmon_lock);
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xe_device_mem_access_put(gt_to_xe(hwmon->gt));
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return count;
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}
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static SENSOR_DEVICE_ATTR(power1_max_interval, 0664,
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xe_hwmon_power1_max_interval_show,
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xe_hwmon_power1_max_interval_store, 0);
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static struct attribute *hwmon_attributes[] = {
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&sensor_dev_attr_power1_max_interval.dev_attr.attr,
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NULL
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};
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static umode_t xe_hwmon_attributes_visible(struct kobject *kobj,
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struct attribute *attr, int index)
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{
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struct device *dev = kobj_to_dev(kobj);
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struct xe_hwmon *hwmon = dev_get_drvdata(dev);
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int ret = 0;
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xe_device_mem_access_get(gt_to_xe(hwmon->gt));
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if (attr == &sensor_dev_attr_power1_max_interval.dev_attr.attr)
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ret = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT) ? attr->mode : 0;
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xe_device_mem_access_put(gt_to_xe(hwmon->gt));
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return ret;
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}
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static const struct attribute_group hwmon_attrgroup = {
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.attrs = hwmon_attributes,
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.is_visible = xe_hwmon_attributes_visible,
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};
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static const struct attribute_group *hwmon_groups[] = {
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&hwmon_attrgroup,
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NULL
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};
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static const struct hwmon_channel_info *hwmon_info[] = {
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HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT),
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HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT),
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@ -569,6 +718,7 @@ xe_hwmon_get_preregistration_info(struct xe_device *xe)
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REG_READ32, &val_sku_unit, 0, 0);
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hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
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hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);
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hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit);
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}
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/*
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@ -615,7 +765,8 @@ void xe_hwmon_register(struct xe_device *xe)
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/* hwmon_dev points to device hwmon<i> */
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hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev, "xe", hwmon,
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&hwmon_chip_info,
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NULL);
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hwmon_groups);
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if (IS_ERR(hwmon->hwmon_dev)) {
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drm_warn(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev);
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xe->hwmon = NULL;
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