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pci-v5.11-fixes-1
-----BEGIN PGP SIGNATURE----- iQJIBAABCgAyFiEEgMe7l+5h9hnxdsnuWYigwDrT+vwFAl/mtVwUHGJoZWxnYWFz QGdvb2dsZS5jb20ACgkQWYigwDrT+vyrUA//U03pKOm8jDCakFGGZlnTNOe31fAz inaR5a7XvGVeFhQcc7GR5Vi5a6dtuwv5hLg78SflNH8F5A29C57xsaygxmLXXzN5 ReLMzvEgtOKS6OPkVXZAHGm6S2H+zKVLhOZB9xhTiCAFsESh8T9O8KVmdWiWz1rE zASlWivMIkkxQjlnsu1a4ZKRdL1zjdFwDQWlQHCVhdpuEdL0fULF49gLhwCF2dGP DmZ1Rd28HDjdtVYoK/EBfGVRiwp7e5Am1sK7AtcbiT+r7Q2uuWVNW09Y3TJrrIEr 05L3liG/QxpSXxLv3KwEMb2jlJl2PQC5YMkItoibJquTCeIvnKWKOvf8rsJqgv2B xLT22okthFSUv60K52n0RoI49IYgcmA7PGUrffO1yfDWjLDoid17wIQ6RJ3j/NdB DLy6OQ1Xnk0uzGIGnZZPue+Rfhwtbc3ZkZ+fBL20BRAF/h7jyhXU+DQYan/p2CRc qmLey3Dm9q8gRJA5RFewqM9UMf3IuWB3VkoZxhWOPNOHaY4qPpAYNoboEjm8vHV6 LCr2ntuTYrXGZHh04EsDyoBtt3z+fWmBxu5iNW811amD2+s4h5UxjpBoBFJjwAux j6qkMSkzp9n01F1WpUhAa7Mb2eAl5hz19J6bihbkS+SbUXO9F2naMA3aplDh2WRg RuJaEoC41d9mTuE= =giDR -----END PGP SIGNATURE----- Merge tag 'pci-v5.11-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI fixes from Bjorn Helgaas: - Fix a tegra enumeration regression (Rob Herring) - Fix a designware-host check that warned on *success*, not failure (Alexander Lobakin) * tag 'pci-v5.11-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: PCI: dwc: Fix inverted condition of DMA mask setup warning PCI: tegra: Fix host link initialization
This commit is contained in:
commit
40f78232f9
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@ -397,12 +397,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
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pp);
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ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32));
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if (!ret) {
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dev_warn(pci->dev,
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"Failed to set DMA mask to 32-bit. "
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"Devices with only 32-bit MSI support"
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" may not work properly\n");
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}
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if (ret)
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dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
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pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg,
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sizeof(pp->msi_msg),
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@ -853,12 +853,14 @@ static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie)
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dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
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}
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static void tegra_pcie_prepare_host(struct pcie_port *pp)
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static int tegra_pcie_dw_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
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u32 val;
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pp->bridge->ops = &tegra_pci_ops;
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if (!pcie->pcie_cap_base)
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pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
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PCI_CAP_ID_EXP);
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@ -907,10 +909,24 @@ static void tegra_pcie_prepare_host(struct pcie_port *pp)
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dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val);
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}
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dw_pcie_setup_rc(pp);
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clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
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return 0;
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}
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static int tegra_pcie_dw_start_link(struct dw_pcie *pci)
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{
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u32 val, offset, speed, tmp;
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struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
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struct pcie_port *pp = &pci->pp;
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bool retry = true;
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if (pcie->mode == DW_PCIE_EP_TYPE) {
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enable_irq(pcie->pex_rst_irq);
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return 0;
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}
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retry_link:
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/* Assert RST */
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val = appl_readl(pcie, APPL_PINMUX);
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val &= ~APPL_PINMUX_PEX_RST;
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@ -929,19 +945,10 @@ static void tegra_pcie_prepare_host(struct pcie_port *pp)
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appl_writel(pcie, val, APPL_PINMUX);
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msleep(100);
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}
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static int tegra_pcie_dw_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
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u32 val, tmp, offset, speed;
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pp->bridge->ops = &tegra_pci_ops;
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tegra_pcie_prepare_host(pp);
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if (dw_pcie_wait_for_link(pci)) {
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if (!retry)
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return 0;
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/*
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* There are some endpoints which can't get the link up if
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* root port has Data Link Feature (DLF) enabled.
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@ -975,10 +982,11 @@ static int tegra_pcie_dw_host_init(struct pcie_port *pp)
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val &= ~PCI_DLF_EXCHANGE_ENABLE;
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dw_pcie_writel_dbi(pci, offset, val);
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tegra_pcie_prepare_host(pp);
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tegra_pcie_dw_host_init(pp);
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dw_pcie_setup_rc(pp);
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if (dw_pcie_wait_for_link(pci))
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return 0;
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retry = false;
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goto retry_link;
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}
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speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) &
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@ -998,15 +1006,6 @@ static int tegra_pcie_dw_link_up(struct dw_pcie *pci)
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return !!(val & PCI_EXP_LNKSTA_DLLLA);
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}
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static int tegra_pcie_dw_start_link(struct dw_pcie *pci)
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{
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struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
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enable_irq(pcie->pex_rst_irq);
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return 0;
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}
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static void tegra_pcie_dw_stop_link(struct dw_pcie *pci)
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{
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struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
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@ -2215,6 +2214,10 @@ static int tegra_pcie_dw_resume_noirq(struct device *dev)
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goto fail_host_init;
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}
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ret = tegra_pcie_dw_start_link(&pcie->pci);
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if (ret < 0)
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goto fail_host_init;
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/* Restore MSI interrupt vector */
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dw_pcie_writel_dbi(&pcie->pci, PORT_LOGIC_MSI_CTRL_INT_0_EN,
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pcie->msi_ctrl_int);
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