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net/mlx5: DR, Refactor ICMP STE builder

Browse source 
Reworked ICMP tag builder to better handle ICMP v4/6 fields and avoid unneeded
code duplication and 'if' statements, removed unused macro, changed bitfield
of len 8 to u8.

Signed-off-by: Alex Vesker <valex@nvidia.com>
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Saeed Mahameed <saeedm@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
This commit is contained in:
Yevgeny Kliteynik 2020-09-22 04:22:24 +03:00 committed by Saeed Mahameed
parent dd2d3c8d20
commit 40ca842c2b
2 changed files with 23 additions and 42 deletions
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57
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c
View file

@ -662,9 +662,8 @@ dr_ste_v0_build_tnl_mpls_init(struct mlx5dr_ste_build *sb,
sb->ste_build_tag_func = &dr_ste_v0_build_tnl_mpls_tag;
}
#define ICMP_TYPE_OFFSET_FIRST_DW 24
#define ICMP_CODE_OFFSET_FIRST_DW 16
#define ICMP_HEADER_DATA_OFFSET_SECOND_DW 0
#define ICMP_TYPE_OFFSET_FIRST_DW 24
#define ICMP_CODE_OFFSET_FIRST_DW 16
static int
dr_ste_v0_build_icmp_tag(struct mlx5dr_match_param *value,
@ -672,49 +671,36 @@ dr_ste_v0_build_icmp_tag(struct mlx5dr_match_param *value,
u8 *tag)
{
struct mlx5dr_match_misc3 *misc_3 = &value->misc3;
u32 icmp_header_data;
u32 *icmp_header_data;
int dw0_location;
int dw1_location;
u32 icmp_type;
u32 icmp_code;
u8 *icmp_type;
u8 *icmp_code;
bool is_ipv4;
is_ipv4 = DR_MASK_IS_ICMPV4_SET(misc_3);
if (is_ipv4) {
icmp_header_data = misc_3->icmpv4_header_data;
icmp_type = misc_3->icmpv4_type;
icmp_code = misc_3->icmpv4_code;
icmp_header_data = &misc_3->icmpv4_header_data;
icmp_type = &misc_3->icmpv4_type;
icmp_code = &misc_3->icmpv4_code;
dw0_location = sb->caps->flex_parser_id_icmp_dw0;
dw1_location = sb->caps->flex_parser_id_icmp_dw1;
} else {
icmp_header_data = misc_3->icmpv6_header_data;
icmp_type = misc_3->icmpv6_type;
icmp_code = misc_3->icmpv6_code;
icmp_header_data = &misc_3->icmpv6_header_data;
icmp_type = &misc_3->icmpv6_type;
icmp_code = &misc_3->icmpv6_code;
dw0_location = sb->caps->flex_parser_id_icmpv6_dw0;
dw1_location = sb->caps->flex_parser_id_icmpv6_dw1;
}
switch (dw0_location) {
case 4:
if (icmp_type) {
MLX5_SET(ste_flex_parser_1, tag, flex_parser_4,
(icmp_type << ICMP_TYPE_OFFSET_FIRST_DW));
if (is_ipv4)
misc_3->icmpv4_type = 0;
else
misc_3->icmpv6_type = 0;
}
MLX5_SET(ste_flex_parser_1, tag, flex_parser_4,
(*icmp_type << ICMP_TYPE_OFFSET_FIRST_DW) |
(*icmp_code << ICMP_TYPE_OFFSET_FIRST_DW));
if (icmp_code) {
u32 cur_val = MLX5_GET(ste_flex_parser_1, tag,
flex_parser_4);
MLX5_SET(ste_flex_parser_1, tag, flex_parser_4,
cur_val | (icmp_code << ICMP_CODE_OFFSET_FIRST_DW));
if (is_ipv4)
misc_3->icmpv4_code = 0;
else
misc_3->icmpv6_code = 0;
}
*icmp_type = 0;
*icmp_code = 0;
break;
default:
return -EINVAL;
@ -722,14 +708,9 @@ dr_ste_v0_build_icmp_tag(struct mlx5dr_match_param *value,
switch (dw1_location) {
case 5:
if (icmp_header_data) {
MLX5_SET(ste_flex_parser_1, tag, flex_parser_5,
(icmp_header_data << ICMP_HEADER_DATA_OFFSET_SECOND_DW));
if (is_ipv4)
misc_3->icmpv4_header_data = 0;
else
misc_3->icmpv6_header_data = 0;
}
MLX5_SET(ste_flex_parser_1, tag, flex_parser_5,
*icmp_header_data);
*icmp_header_data = 0;
break;
default:
return -EINVAL;

8
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h
View file

@ -596,10 +596,10 @@ struct mlx5dr_match_misc3 {
u32 outer_vxlan_gpe_next_protocol:8;
u32 icmpv4_header_data;
u32 icmpv6_header_data;
u32 icmpv6_code:8;
u32 icmpv6_type:8;
u32 icmpv4_code:8;
u32 icmpv4_type:8;
u8 icmpv6_code;
u8 icmpv6_type;
u8 icmpv4_code;
u8 icmpv4_type;
u8 reserved_auto3[0x1c];
};