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[media] v4l: s5p-tv: hdmi: parametrize DV timings
This patch fixes timings configuration in HDMI register. It adds support for numerous new presets including interlaced ones. Signed-off-by: Tomasz Stanislawski <t.stanislaws@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Tomasz Stanislawski
Mauro Carvalho Chehab
parent
2470ea3f7f
commit
3f468accf2
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@ -42,7 +42,23 @@ MODULE_DESCRIPTION("Samsung HDMI");
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MODULE_LICENSE("GPL");
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/* default preset configured on probe */
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#define HDMI_DEFAULT_PRESET V4L2_DV_1080P60
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#define HDMI_DEFAULT_PRESET V4L2_DV_480P59_94
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struct hdmi_pulse {
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u32 beg;
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u32 end;
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};
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struct hdmi_timings {
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struct hdmi_pulse hact;
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u32 hsyn_pol; /* 0 - high, 1 - low */
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struct hdmi_pulse hsyn;
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u32 interlaced;
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struct hdmi_pulse vact[2];
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u32 vsyn_pol; /* 0 - high, 1 - low */
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u32 vsyn_off;
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struct hdmi_pulse vsyn[2];
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};
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struct hdmi_resources {
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struct clk *hdmi;
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@ -70,64 +86,13 @@ struct hdmi_device {
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/** subdev of MHL interface */
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struct v4l2_subdev *mhl_sd;
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/** configuration of current graphic mode */
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const struct hdmi_preset_conf *cur_conf;
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const struct hdmi_timings *cur_conf;
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/** current preset */
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u32 cur_preset;
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/** other resources */
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struct hdmi_resources res;
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};
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struct hdmi_tg_regs {
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u8 cmd;
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u8 h_fsz_l;
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u8 h_fsz_h;
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u8 hact_st_l;
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u8 hact_st_h;
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u8 hact_sz_l;
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u8 hact_sz_h;
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u8 v_fsz_l;
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u8 v_fsz_h;
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u8 vsync_l;
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u8 vsync_h;
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u8 vsync2_l;
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u8 vsync2_h;
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u8 vact_st_l;
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u8 vact_st_h;
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u8 vact_sz_l;
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u8 vact_sz_h;
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u8 field_chg_l;
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u8 field_chg_h;
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u8 vact_st2_l;
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u8 vact_st2_h;
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u8 vsync_top_hdmi_l;
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u8 vsync_top_hdmi_h;
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u8 vsync_bot_hdmi_l;
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u8 vsync_bot_hdmi_h;
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u8 field_top_hdmi_l;
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u8 field_top_hdmi_h;
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u8 field_bot_hdmi_l;
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u8 field_bot_hdmi_h;
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};
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struct hdmi_core_regs {
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u8 h_blank[2];
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u8 v_blank[3];
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u8 h_v_line[3];
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u8 vsync_pol[1];
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u8 int_pro_mode[1];
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u8 v_blank_f[3];
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u8 h_sync_gen[3];
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u8 v_sync_gen1[3];
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u8 v_sync_gen2[3];
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u8 v_sync_gen3[3];
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};
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struct hdmi_preset_conf {
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struct hdmi_core_regs core;
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struct hdmi_tg_regs tg;
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struct v4l2_mbus_framefmt mbus_fmt;
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};
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static struct platform_device_id hdmi_driver_types[] = {
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{
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.name = "s5pv210-hdmi",
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@ -165,6 +130,21 @@ void hdmi_writeb(struct hdmi_device *hdev, u32 reg_id, u8 value)
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writeb(value, hdev->regs + reg_id);
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}
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static inline
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void hdmi_writebn(struct hdmi_device *hdev, u32 reg_id, int n, u32 value)
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{
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switch (n) {
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default:
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writeb(value >> 24, hdev->regs + reg_id + 12);
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case 3:
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writeb(value >> 16, hdev->regs + reg_id + 8);
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case 2:
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writeb(value >> 8, hdev->regs + reg_id + 4);
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case 1:
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writeb(value >> 0, hdev->regs + reg_id + 0);
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}
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}
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static inline u32 hdmi_read(struct hdmi_device *hdev, u32 reg_id)
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{
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return readl(hdev->regs + reg_id);
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@ -211,72 +191,63 @@ static void hdmi_reg_init(struct hdmi_device *hdev)
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}
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static void hdmi_timing_apply(struct hdmi_device *hdev,
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const struct hdmi_preset_conf *conf)
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const struct hdmi_timings *t)
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{
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const struct hdmi_core_regs *core = &conf->core;
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const struct hdmi_tg_regs *tg = &conf->tg;
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/* setting core registers */
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hdmi_writeb(hdev, HDMI_H_BLANK_0, core->h_blank[0]);
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hdmi_writeb(hdev, HDMI_H_BLANK_1, core->h_blank[1]);
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hdmi_writeb(hdev, HDMI_V_BLANK_0, core->v_blank[0]);
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hdmi_writeb(hdev, HDMI_V_BLANK_1, core->v_blank[1]);
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hdmi_writeb(hdev, HDMI_V_BLANK_2, core->v_blank[2]);
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hdmi_writeb(hdev, HDMI_H_V_LINE_0, core->h_v_line[0]);
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hdmi_writeb(hdev, HDMI_H_V_LINE_1, core->h_v_line[1]);
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hdmi_writeb(hdev, HDMI_H_V_LINE_2, core->h_v_line[2]);
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hdmi_writeb(hdev, HDMI_VSYNC_POL, core->vsync_pol[0]);
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hdmi_writeb(hdev, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
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hdmi_writeb(hdev, HDMI_V_BLANK_F_0, core->v_blank_f[0]);
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hdmi_writeb(hdev, HDMI_V_BLANK_F_1, core->v_blank_f[1]);
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hdmi_writeb(hdev, HDMI_V_BLANK_F_2, core->v_blank_f[2]);
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hdmi_writeb(hdev, HDMI_H_SYNC_GEN_0, core->h_sync_gen[0]);
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hdmi_writeb(hdev, HDMI_H_SYNC_GEN_1, core->h_sync_gen[1]);
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hdmi_writeb(hdev, HDMI_H_SYNC_GEN_2, core->h_sync_gen[2]);
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hdmi_writeb(hdev, HDMI_V_SYNC_GEN_1_0, core->v_sync_gen1[0]);
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hdmi_writeb(hdev, HDMI_V_SYNC_GEN_1_1, core->v_sync_gen1[1]);
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hdmi_writeb(hdev, HDMI_V_SYNC_GEN_1_2, core->v_sync_gen1[2]);
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hdmi_writeb(hdev, HDMI_V_SYNC_GEN_2_0, core->v_sync_gen2[0]);
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hdmi_writeb(hdev, HDMI_V_SYNC_GEN_2_1, core->v_sync_gen2[1]);
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hdmi_writeb(hdev, HDMI_V_SYNC_GEN_2_2, core->v_sync_gen2[2]);
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hdmi_writeb(hdev, HDMI_V_SYNC_GEN_3_0, core->v_sync_gen3[0]);
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hdmi_writeb(hdev, HDMI_V_SYNC_GEN_3_1, core->v_sync_gen3[1]);
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hdmi_writeb(hdev, HDMI_V_SYNC_GEN_3_2, core->v_sync_gen3[2]);
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hdmi_writebn(hdev, HDMI_H_BLANK_0, 2, t->hact.beg);
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hdmi_writebn(hdev, HDMI_H_SYNC_GEN_0, 3,
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(t->hsyn_pol << 20) | (t->hsyn.end << 10) | t->hsyn.beg);
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hdmi_writeb(hdev, HDMI_VSYNC_POL, t->vsyn_pol);
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hdmi_writebn(hdev, HDMI_V_BLANK_0, 3,
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(t->vact[0].beg << 11) | t->vact[0].end);
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hdmi_writebn(hdev, HDMI_V_SYNC_GEN_1_0, 3,
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(t->vsyn[0].beg << 12) | t->vsyn[0].end);
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if (t->interlaced) {
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u32 vsyn_trans = t->hsyn.beg + t->vsyn_off;
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hdmi_writeb(hdev, HDMI_INT_PRO_MODE, 1);
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hdmi_writebn(hdev, HDMI_H_V_LINE_0, 3,
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(t->hact.end << 12) | t->vact[1].end);
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hdmi_writebn(hdev, HDMI_V_BLANK_F_0, 3,
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(t->vact[1].end << 11) | t->vact[1].beg);
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hdmi_writebn(hdev, HDMI_V_SYNC_GEN_2_0, 3,
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(t->vsyn[1].beg << 12) | t->vsyn[1].end);
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hdmi_writebn(hdev, HDMI_V_SYNC_GEN_3_0, 3,
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(vsyn_trans << 12) | vsyn_trans);
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} else {
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hdmi_writeb(hdev, HDMI_INT_PRO_MODE, 0);
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hdmi_writebn(hdev, HDMI_H_V_LINE_0, 3,
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(t->hact.end << 12) | t->vact[0].end);
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}
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/* Timing generator registers */
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hdmi_writeb(hdev, HDMI_TG_H_FSZ_L, tg->h_fsz_l);
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hdmi_writeb(hdev, HDMI_TG_H_FSZ_H, tg->h_fsz_h);
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hdmi_writeb(hdev, HDMI_TG_HACT_ST_L, tg->hact_st_l);
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hdmi_writeb(hdev, HDMI_TG_HACT_ST_H, tg->hact_st_h);
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hdmi_writeb(hdev, HDMI_TG_HACT_SZ_L, tg->hact_sz_l);
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hdmi_writeb(hdev, HDMI_TG_HACT_SZ_H, tg->hact_sz_h);
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hdmi_writeb(hdev, HDMI_TG_V_FSZ_L, tg->v_fsz_l);
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hdmi_writeb(hdev, HDMI_TG_V_FSZ_H, tg->v_fsz_h);
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hdmi_writeb(hdev, HDMI_TG_VSYNC_L, tg->vsync_l);
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hdmi_writeb(hdev, HDMI_TG_VSYNC_H, tg->vsync_h);
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hdmi_writeb(hdev, HDMI_TG_VSYNC2_L, tg->vsync2_l);
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hdmi_writeb(hdev, HDMI_TG_VSYNC2_H, tg->vsync2_h);
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hdmi_writeb(hdev, HDMI_TG_VACT_ST_L, tg->vact_st_l);
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hdmi_writeb(hdev, HDMI_TG_VACT_ST_H, tg->vact_st_h);
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hdmi_writeb(hdev, HDMI_TG_VACT_SZ_L, tg->vact_sz_l);
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hdmi_writeb(hdev, HDMI_TG_VACT_SZ_H, tg->vact_sz_h);
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hdmi_writeb(hdev, HDMI_TG_FIELD_CHG_L, tg->field_chg_l);
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hdmi_writeb(hdev, HDMI_TG_FIELD_CHG_H, tg->field_chg_h);
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hdmi_writeb(hdev, HDMI_TG_VACT_ST2_L, tg->vact_st2_l);
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hdmi_writeb(hdev, HDMI_TG_VACT_ST2_H, tg->vact_st2_h);
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hdmi_writeb(hdev, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi_l);
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hdmi_writeb(hdev, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi_h);
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hdmi_writeb(hdev, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi_l);
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hdmi_writeb(hdev, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi_h);
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hdmi_writeb(hdev, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi_l);
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hdmi_writeb(hdev, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi_h);
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hdmi_writeb(hdev, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi_l);
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hdmi_writeb(hdev, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi_h);
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hdmi_writebn(hdev, HDMI_TG_H_FSZ_L, 2, t->hact.end);
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hdmi_writebn(hdev, HDMI_TG_HACT_ST_L, 2, t->hact.beg);
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hdmi_writebn(hdev, HDMI_TG_HACT_SZ_L, 2, t->hact.end - t->hact.beg);
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hdmi_writebn(hdev, HDMI_TG_VSYNC_L, 2, t->vsyn[0].beg);
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hdmi_writebn(hdev, HDMI_TG_VACT_ST_L, 2, t->vact[0].beg);
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hdmi_writebn(hdev, HDMI_TG_VACT_SZ_L, 2,
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t->vact[0].end - t->vact[0].beg);
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hdmi_writebn(hdev, HDMI_TG_VSYNC_TOP_HDMI_L, 2, t->vsyn[0].beg);
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hdmi_writebn(hdev, HDMI_TG_FIELD_TOP_HDMI_L, 2, t->vsyn[0].beg);
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if (t->interlaced) {
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hdmi_write_mask(hdev, HDMI_TG_CMD, ~0, HDMI_TG_FIELD_EN);
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hdmi_writebn(hdev, HDMI_TG_V_FSZ_L, 2, t->vact[1].end);
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hdmi_writebn(hdev, HDMI_TG_VSYNC2_L, 2, t->vsyn[1].beg);
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hdmi_writebn(hdev, HDMI_TG_FIELD_CHG_L, 2, t->vact[0].end);
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hdmi_writebn(hdev, HDMI_TG_VACT_ST2_L, 2, t->vact[1].beg);
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hdmi_writebn(hdev, HDMI_TG_VSYNC_BOT_HDMI_L, 2, t->vsyn[1].beg);
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hdmi_writebn(hdev, HDMI_TG_FIELD_BOT_HDMI_L, 2, t->vsyn[1].beg);
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} else {
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hdmi_write_mask(hdev, HDMI_TG_CMD, 0, HDMI_TG_FIELD_EN);
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hdmi_writebn(hdev, HDMI_TG_V_FSZ_L, 2, t->vact[0].end);
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}
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}
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static int hdmi_conf_apply(struct hdmi_device *hdmi_dev)
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{
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struct device *dev = hdmi_dev->dev;
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const struct hdmi_preset_conf *conf = hdmi_dev->cur_conf;
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const struct hdmi_timings *conf = hdmi_dev->cur_conf;
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struct v4l2_dv_preset preset;
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int ret;
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@ -398,156 +369,126 @@ static void hdmi_dumpregs(struct hdmi_device *hdev, char *prefix)
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#undef DUMPREG
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}
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static const struct hdmi_preset_conf hdmi_conf_480p = {
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.core = {
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.h_blank = {0x8a, 0x00},
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.v_blank = {0x0d, 0x6a, 0x01},
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.h_v_line = {0x0d, 0xa2, 0x35},
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.vsync_pol = {0x01},
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.int_pro_mode = {0x00},
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.v_blank_f = {0x00, 0x00, 0x00},
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.h_sync_gen = {0x0e, 0x30, 0x11},
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.v_sync_gen1 = {0x0f, 0x90, 0x00},
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/* other don't care */
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},
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.tg = {
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0x00, /* cmd */
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0x5a, 0x03, /* h_fsz */
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0x8a, 0x00, 0xd0, 0x02, /* hact */
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0x0d, 0x02, /* v_fsz */
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0x01, 0x00, 0x33, 0x02, /* vsync */
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0x2d, 0x00, 0xe0, 0x01, /* vact */
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0x33, 0x02, /* field_chg */
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0x49, 0x02, /* vact_st2 */
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0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
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0x01, 0x00, 0x33, 0x02, /* field top/bot */
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},
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.mbus_fmt = {
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.width = 720,
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.height = 480,
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.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
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.field = V4L2_FIELD_NONE,
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.colorspace = V4L2_COLORSPACE_SRGB,
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},
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static const struct hdmi_timings hdmi_timings_480p = {
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.hact = { .beg = 138, .end = 858 },
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.hsyn_pol = 1,
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.hsyn = { .beg = 16, .end = 16 + 62 },
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.interlaced = 0,
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.vact[0] = { .beg = 42 + 3, .end = 522 + 3 },
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.vsyn_pol = 1,
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.vsyn[0] = { .beg = 6 + 3, .end = 12 + 3},
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};
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static const struct hdmi_preset_conf hdmi_conf_720p60 = {
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.core = {
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.h_blank = {0x72, 0x01},
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.v_blank = {0xee, 0xf2, 0x00},
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.h_v_line = {0xee, 0x22, 0x67},
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.vsync_pol = {0x00},
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.int_pro_mode = {0x00},
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.v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
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.h_sync_gen = {0x6c, 0x50, 0x02},
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.v_sync_gen1 = {0x0a, 0x50, 0x00},
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/* other don't care */
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},
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.tg = {
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0x00, /* cmd */
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0x72, 0x06, /* h_fsz */
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0x72, 0x01, 0x00, 0x05, /* hact */
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0xee, 0x02, /* v_fsz */
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0x01, 0x00, 0x33, 0x02, /* vsync */
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0x1e, 0x00, 0xd0, 0x02, /* vact */
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0x33, 0x02, /* field_chg */
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0x49, 0x02, /* vact_st2 */
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0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
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0x01, 0x00, 0x33, 0x02, /* field top/bot */
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},
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.mbus_fmt = {
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.width = 1280,
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.height = 720,
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.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
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.field = V4L2_FIELD_NONE,
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.colorspace = V4L2_COLORSPACE_SRGB,
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},
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static const struct hdmi_timings hdmi_timings_576p50 = {
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.hact = { .beg = 144, .end = 864 },
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.hsyn_pol = 1,
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.hsyn = { .beg = 12, .end = 12 + 64 },
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.interlaced = 0,
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.vact[0] = { .beg = 44 + 5, .end = 620 + 5 },
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.vsyn_pol = 1,
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.vsyn[0] = { .beg = 0 + 5, .end = 5 + 5},
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};
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|
||||
static const struct hdmi_preset_conf hdmi_conf_1080p50 = {
|
||||
.core = {
|
||||
.h_blank = {0xd0, 0x02},
|
||||
.v_blank = {0x65, 0x6c, 0x01},
|
||||
.h_v_line = {0x65, 0x04, 0xa5},
|
||||
.vsync_pol = {0x00},
|
||||
.int_pro_mode = {0x00},
|
||||
.v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
|
||||
.h_sync_gen = {0x0e, 0xea, 0x08},
|
||||
.v_sync_gen1 = {0x09, 0x40, 0x00},
|
||||
/* other don't care */
|
||||
},
|
||||
.tg = {
|
||||
0x00, /* cmd */
|
||||
0x98, 0x08, /* h_fsz */
|
||||
0x18, 0x01, 0x80, 0x07, /* hact */
|
||||
0x65, 0x04, /* v_fsz */
|
||||
0x01, 0x00, 0x33, 0x02, /* vsync */
|
||||
0x2d, 0x00, 0x38, 0x04, /* vact */
|
||||
0x33, 0x02, /* field_chg */
|
||||
0x49, 0x02, /* vact_st2 */
|
||||
0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
|
||||
0x01, 0x00, 0x33, 0x02, /* field top/bot */
|
||||
},
|
||||
.mbus_fmt = {
|
||||
.width = 1920,
|
||||
.height = 1080,
|
||||
.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
|
||||
.field = V4L2_FIELD_NONE,
|
||||
.colorspace = V4L2_COLORSPACE_SRGB,
|
||||
},
|
||||
static const struct hdmi_timings hdmi_timings_720p60 = {
|
||||
.hact = { .beg = 370, .end = 1650 },
|
||||
.hsyn_pol = 0,
|
||||
.hsyn = { .beg = 110, .end = 110 + 40 },
|
||||
.interlaced = 0,
|
||||
.vact[0] = { .beg = 25 + 5, .end = 745 + 5 },
|
||||
.vsyn_pol = 0,
|
||||
.vsyn[0] = { .beg = 0 + 5, .end = 5 + 5},
|
||||
};
|
||||
|
||||
static const struct hdmi_preset_conf hdmi_conf_1080p60 = {
|
||||
.core = {
|
||||
.h_blank = {0x18, 0x01},
|
||||
.v_blank = {0x65, 0x6c, 0x01},
|
||||
.h_v_line = {0x65, 0x84, 0x89},
|
||||
.vsync_pol = {0x00},
|
||||
.int_pro_mode = {0x00},
|
||||
.v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
|
||||
.h_sync_gen = {0x56, 0x08, 0x02},
|
||||
.v_sync_gen1 = {0x09, 0x40, 0x00},
|
||||
/* other don't care */
|
||||
},
|
||||
.tg = {
|
||||
0x00, /* cmd */
|
||||
0x98, 0x08, /* h_fsz */
|
||||
0x18, 0x01, 0x80, 0x07, /* hact */
|
||||
0x65, 0x04, /* v_fsz */
|
||||
0x01, 0x00, 0x33, 0x02, /* vsync */
|
||||
0x2d, 0x00, 0x38, 0x04, /* vact */
|
||||
0x33, 0x02, /* field_chg */
|
||||
0x48, 0x02, /* vact_st2 */
|
||||
0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
|
||||
0x01, 0x00, 0x33, 0x02, /* field top/bot */
|
||||
},
|
||||
.mbus_fmt = {
|
||||
.width = 1920,
|
||||
.height = 1080,
|
||||
.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
|
||||
.field = V4L2_FIELD_NONE,
|
||||
.colorspace = V4L2_COLORSPACE_SRGB,
|
||||
},
|
||||
static const struct hdmi_timings hdmi_timings_720p50 = {
|
||||
.hact = { .beg = 700, .end = 1980 },
|
||||
.hsyn_pol = 0,
|
||||
.hsyn = { .beg = 440, .end = 440 + 40 },
|
||||
.interlaced = 0,
|
||||
.vact[0] = { .beg = 25 + 5, .end = 745 + 5 },
|
||||
.vsyn_pol = 0,
|
||||
.vsyn[0] = { .beg = 0 + 5, .end = 5 + 5},
|
||||
};
|
||||
|
||||
static const struct hdmi_timings hdmi_timings_1080p24 = {
|
||||
.hact = { .beg = 830, .end = 2750 },
|
||||
.hsyn_pol = 0,
|
||||
.hsyn = { .beg = 638, .end = 638 + 44 },
|
||||
.interlaced = 0,
|
||||
.vact[0] = { .beg = 41 + 4, .end = 1121 + 4 },
|
||||
.vsyn_pol = 0,
|
||||
.vsyn[0] = { .beg = 0 + 4, .end = 5 + 4},
|
||||
};
|
||||
|
||||
static const struct hdmi_timings hdmi_timings_1080p60 = {
|
||||
.hact = { .beg = 280, .end = 2200 },
|
||||
.hsyn_pol = 0,
|
||||
.hsyn = { .beg = 88, .end = 88 + 44 },
|
||||
.interlaced = 0,
|
||||
.vact[0] = { .beg = 41 + 4, .end = 1121 + 4 },
|
||||
.vsyn_pol = 0,
|
||||
.vsyn[0] = { .beg = 0 + 4, .end = 5 + 4},
|
||||
};
|
||||
|
||||
static const struct hdmi_timings hdmi_timings_1080i60 = {
|
||||
.hact = { .beg = 280, .end = 2200 },
|
||||
.hsyn_pol = 0,
|
||||
.hsyn = { .beg = 88, .end = 88 + 44 },
|
||||
.interlaced = 1,
|
||||
.vact[0] = { .beg = 20 + 2, .end = 560 + 2 },
|
||||
.vact[1] = { .beg = 583 + 2, .end = 1123 + 2 },
|
||||
.vsyn_pol = 0,
|
||||
.vsyn_off = 1100,
|
||||
.vsyn[0] = { .beg = 0 + 2, .end = 5 + 2},
|
||||
.vsyn[1] = { .beg = 562 + 2, .end = 567 + 2},
|
||||
};
|
||||
|
||||
static const struct hdmi_timings hdmi_timings_1080i50 = {
|
||||
.hact = { .beg = 720, .end = 2640 },
|
||||
.hsyn_pol = 0,
|
||||
.hsyn = { .beg = 528, .end = 528 + 44 },
|
||||
.interlaced = 1,
|
||||
.vact[0] = { .beg = 20 + 2, .end = 560 + 2 },
|
||||
.vact[1] = { .beg = 583 + 2, .end = 1123 + 2 },
|
||||
.vsyn_pol = 0,
|
||||
.vsyn_off = 1320,
|
||||
.vsyn[0] = { .beg = 0 + 2, .end = 5 + 2},
|
||||
.vsyn[1] = { .beg = 562 + 2, .end = 567 + 2},
|
||||
};
|
||||
|
||||
static const struct hdmi_timings hdmi_timings_1080p50 = {
|
||||
.hact = { .beg = 720, .end = 2640 },
|
||||
.hsyn_pol = 0,
|
||||
.hsyn = { .beg = 528, .end = 528 + 44 },
|
||||
.interlaced = 0,
|
||||
.vact[0] = { .beg = 41 + 4, .end = 1121 + 4 },
|
||||
.vsyn_pol = 0,
|
||||
.vsyn[0] = { .beg = 0 + 4, .end = 5 + 4},
|
||||
};
|
||||
|
||||
static const struct {
|
||||
u32 preset;
|
||||
const struct hdmi_preset_conf *conf;
|
||||
} hdmi_conf[] = {
|
||||
{ V4L2_DV_480P59_94, &hdmi_conf_480p },
|
||||
{ V4L2_DV_720P59_94, &hdmi_conf_720p60 },
|
||||
{ V4L2_DV_1080P50, &hdmi_conf_1080p50 },
|
||||
{ V4L2_DV_1080P30, &hdmi_conf_1080p60 },
|
||||
{ V4L2_DV_1080P60, &hdmi_conf_1080p60 },
|
||||
const struct hdmi_timings *timings;
|
||||
} hdmi_timings[] = {
|
||||
{ V4L2_DV_480P59_94, &hdmi_timings_480p },
|
||||
{ V4L2_DV_576P50, &hdmi_timings_576p50 },
|
||||
{ V4L2_DV_720P50, &hdmi_timings_720p50 },
|
||||
{ V4L2_DV_720P59_94, &hdmi_timings_720p60 },
|
||||
{ V4L2_DV_720P60, &hdmi_timings_720p60 },
|
||||
{ V4L2_DV_1080P24, &hdmi_timings_1080p24 },
|
||||
{ V4L2_DV_1080P30, &hdmi_timings_1080p60 },
|
||||
{ V4L2_DV_1080P50, &hdmi_timings_1080p50 },
|
||||
{ V4L2_DV_1080I50, &hdmi_timings_1080i50 },
|
||||
{ V4L2_DV_1080I60, &hdmi_timings_1080i60 },
|
||||
{ V4L2_DV_1080P60, &hdmi_timings_1080p60 },
|
||||
};
|
||||
|
||||
static const struct hdmi_preset_conf *hdmi_preset2conf(u32 preset)
|
||||
static const struct hdmi_timings *hdmi_preset2timings(u32 preset)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(hdmi_conf); ++i)
|
||||
if (hdmi_conf[i].preset == preset)
|
||||
return hdmi_conf[i].conf;
|
||||
for (i = 0; i < ARRAY_SIZE(hdmi_timings); ++i)
|
||||
if (hdmi_timings[i].preset == preset)
|
||||
return hdmi_timings[i].timings;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
|
@ -671,9 +612,9 @@ static int hdmi_s_dv_preset(struct v4l2_subdev *sd,
|
|||
{
|
||||
struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
|
||||
struct device *dev = hdev->dev;
|
||||
const struct hdmi_preset_conf *conf;
|
||||
const struct hdmi_timings *conf;
|
||||
|
||||
conf = hdmi_preset2conf(preset->preset);
|
||||
conf = hdmi_preset2timings(preset->preset);
|
||||
if (conf == NULL) {
|
||||
dev_err(dev, "preset (%u) not supported\n", preset->preset);
|
||||
return -EINVAL;
|
||||
|
|
@ -695,21 +636,32 @@ static int hdmi_g_mbus_fmt(struct v4l2_subdev *sd,
|
|||
struct v4l2_mbus_framefmt *fmt)
|
||||
{
|
||||
struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
|
||||
struct device *dev = hdev->dev;
|
||||
const struct hdmi_timings *t = hdev->cur_conf;
|
||||
|
||||
dev_dbg(dev, "%s\n", __func__);
|
||||
dev_dbg(hdev->dev, "%s\n", __func__);
|
||||
if (!hdev->cur_conf)
|
||||
return -EINVAL;
|
||||
*fmt = hdev->cur_conf->mbus_fmt;
|
||||
memset(fmt, 0, sizeof *fmt);
|
||||
fmt->width = t->hact.end - t->hact.beg;
|
||||
fmt->height = t->vact[0].end - t->vact[0].beg;
|
||||
fmt->code = V4L2_MBUS_FMT_FIXED; /* means RGB888 */
|
||||
fmt->colorspace = V4L2_COLORSPACE_SRGB;
|
||||
if (t->interlaced) {
|
||||
fmt->field = V4L2_FIELD_INTERLACED;
|
||||
fmt->height *= 2;
|
||||
} else {
|
||||
fmt->field = V4L2_FIELD_NONE;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hdmi_enum_dv_presets(struct v4l2_subdev *sd,
|
||||
struct v4l2_dv_enum_preset *preset)
|
||||
{
|
||||
if (preset->index >= ARRAY_SIZE(hdmi_conf))
|
||||
if (preset->index >= ARRAY_SIZE(hdmi_timings))
|
||||
return -EINVAL;
|
||||
return v4l_fill_dv_preset_info(hdmi_conf[preset->index].preset, preset);
|
||||
return v4l_fill_dv_preset_info(hdmi_timings[preset->index].preset,
|
||||
preset);
|
||||
}
|
||||
|
||||
static const struct v4l2_subdev_core_ops hdmi_sd_core_ops = {
|
||||
|
|
@ -993,7 +945,7 @@ static int __devinit hdmi_probe(struct platform_device *pdev)
|
|||
strlcpy(sd->name, "s5p-hdmi", sizeof sd->name);
|
||||
hdmi_dev->cur_preset = HDMI_DEFAULT_PRESET;
|
||||
/* FIXME: missing fail preset is not supported */
|
||||
hdmi_dev->cur_conf = hdmi_preset2conf(hdmi_dev->cur_preset);
|
||||
hdmi_dev->cur_conf = hdmi_preset2timings(hdmi_dev->cur_preset);
|
||||
|
||||
/* storing subdev for call that have only access to struct device */
|
||||
dev_set_drvdata(dev, sd);
|
||||
|
|
|
|||
|
|
@ -140,6 +140,7 @@
|
|||
#define HDMI_MODE_MASK (3 << 0)
|
||||
|
||||
/* HDMI_TG_CMD */
|
||||
#define HDMI_TG_FIELD_EN (1 << 1)
|
||||
#define HDMI_TG_EN (1 << 0)
|
||||
|
||||
#endif /* SAMSUNG_REGS_HDMI_H */
|
||||
|
|
|
|||
Loading…
Reference in a new issue