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tools arch x86: Sync the msr-index.h copy with the kernel sources
To pick up the changes from these csets:
8c29f01654
("x86/sev: Add SEV-SNP guest feature negotiation support")
That cause no changes to tooling:
$ tools/perf/trace/beauty/tracepoints/x86_msr.sh > before
$ cp arch/x86/include/asm/msr-index.h tools/arch/x86/include/asm/msr-index.h
$ tools/perf/trace/beauty/tracepoints/x86_msr.sh > after
$ diff -u before after
$
Just silences this perf build warning:
Warning: Kernel ABI header at 'tools/arch/x86/include/asm/msr-index.h' differs from latest version at 'arch/x86/include/asm/msr-index.h'
diff -u tools/arch/x86/include/asm/msr-index.h arch/x86/include/asm/msr-index.h
Cc: Borislav Petkov (AMD) <bp@alien8.de>
Cc: Nikunj A Dadhania <nikunj@amd.com>
Link: https://lore.kernel.org/lkml/Y%2FZrNvtcijPWagCp@kernel.org/
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
parent
b48279af63
commit
3ef9fec011
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@ -566,6 +566,26 @@
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#define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT)
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#define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT)
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/* SNP feature bits enabled by the hypervisor */
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#define MSR_AMD64_SNP_VTOM BIT_ULL(3)
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#define MSR_AMD64_SNP_REFLECT_VC BIT_ULL(4)
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#define MSR_AMD64_SNP_RESTRICTED_INJ BIT_ULL(5)
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#define MSR_AMD64_SNP_ALT_INJ BIT_ULL(6)
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#define MSR_AMD64_SNP_DEBUG_SWAP BIT_ULL(7)
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#define MSR_AMD64_SNP_PREVENT_HOST_IBS BIT_ULL(8)
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#define MSR_AMD64_SNP_BTB_ISOLATION BIT_ULL(9)
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#define MSR_AMD64_SNP_VMPL_SSS BIT_ULL(10)
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#define MSR_AMD64_SNP_SECURE_TSC BIT_ULL(11)
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#define MSR_AMD64_SNP_VMGEXIT_PARAM BIT_ULL(12)
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#define MSR_AMD64_SNP_IBS_VIRT BIT_ULL(14)
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#define MSR_AMD64_SNP_VMSA_REG_PROTECTION BIT_ULL(16)
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#define MSR_AMD64_SNP_SMT_PROTECTION BIT_ULL(17)
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/* SNP feature bits reserved for future use. */
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#define MSR_AMD64_SNP_RESERVED_BIT13 BIT_ULL(13)
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#define MSR_AMD64_SNP_RESERVED_BIT15 BIT_ULL(15)
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#define MSR_AMD64_SNP_RESERVED_MASK GENMASK_ULL(63, 18)
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#define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f
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/* AMD Collaborative Processor Performance Control MSRs */
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