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powerpc/fsl: Support unique MSI addresses per PCIe Root Complex

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Its feasible based on how the PCI address map is setup that the region
of PCI address space used for MSIs differs for each PHB on the same SoC.

Instead of assuming that the address mappes to CCSRBAR 1:1 we read
PEXCSRBAR (BAR0) for the PHB that the given pci_dev is on.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2009-05-12 15:51:56 -05:00
parent 12ac426f88
commit 3da34aae03
1 changed files with 7 additions and 2 deletions
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9
arch/powerpc/sysdev/fsl_msi.c
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@ -113,8 +113,13 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
struct msi_msg *msg) struct msi_msg *msg)
{ {
struct fsl_msi *msi_data = fsl_msi; struct fsl_msi *msi_data = fsl_msi;
struct pci_controller *hose = pci_bus_to_host(pdev->bus);
u32 base = 0;
msg->address_lo = msi_data->msi_addr_lo; pci_bus_read_config_dword(hose->bus,
PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
msg->address_lo = msi_data->msi_addr_lo + base;
msg->address_hi = msi_data->msi_addr_hi; msg->address_hi = msi_data->msi_addr_hi;
msg->data = hwirq; msg->data = hwirq;
@ -271,7 +276,7 @@ static int __devinit fsl_of_msi_probe(struct of_device *dev,
msi->irqhost->host_data = msi; msi->irqhost->host_data = msi;
msi->msi_addr_hi = 0x0; msi->msi_addr_hi = 0x0;
msi->msi_addr_lo = res.start + features->msiir_offset; msi->msi_addr_lo = features->msiir_offset + (res.start & 0xfffff);
rc = fsl_msi_init_allocator(msi); rc = fsl_msi_init_allocator(msi);
if (rc) { if (rc) {