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MIPS: CPS: Cluster support for topology functions
Modify the functions we use to read information about the topology of the system (the number of cores, VPs & IOCUs that it contains) in order to take into account multiple clusters, and provide a new function to determine the number of clusters in the system. Users of these functions are modified only such that they continue to build successfully - having them actually handle multiple clusters is left to further patches. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17016/ Patchwork: https://patchwork.linux-mips.org/patch/17218/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -2365,7 +2365,6 @@ config MIPS_CPS
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bool "MIPS Coherent Processing System support"
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bool "MIPS Coherent Processing System support"
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depends on SYS_SUPPORTS_MIPS_CPS
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depends on SYS_SUPPORTS_MIPS_CPS
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select MIPS_CM
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select MIPS_CM
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select MIPS_CPC
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select MIPS_CPS_PM if HOTPLUG_CPU
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select MIPS_CPS_PM if HOTPLUG_CPU
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select SMP
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select SMP
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select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
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select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
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@ -2382,11 +2381,11 @@ config MIPS_CPS
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config MIPS_CPS_PM
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config MIPS_CPS_PM
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depends on MIPS_CPS
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depends on MIPS_CPS
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select MIPS_CPC
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bool
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bool
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config MIPS_CM
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config MIPS_CM
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bool
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bool
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select MIPS_CPC
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config MIPS_CPC
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config MIPS_CPC
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bool
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bool
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@ -328,36 +328,6 @@ GCR_CX_ACCESSOR_RW(32, 0x030, reset_ext_base)
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#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA GENMASK(7, 1)
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#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA GENMASK(7, 1)
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#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT BIT(0)
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#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT BIT(0)
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/**
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* mips_cm_numcores - return the number of cores present in the system
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*
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* Returns the value of the PCORES field of the GCR_CONFIG register plus 1, or
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* zero if no Coherence Manager is present.
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*/
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static inline unsigned mips_cm_numcores(void)
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{
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if (!mips_cm_present())
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return 0;
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return ((read_gcr_config() & CM_GCR_CONFIG_PCORES)
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>> __ffs(CM_GCR_CONFIG_PCORES)) + 1;
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}
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/**
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* mips_cm_numiocu - return the number of IOCUs present in the system
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*
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* Returns the value of the NUMIOCU field of the GCR_CONFIG register, or zero
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* if no Coherence Manager is present.
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*/
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static inline unsigned mips_cm_numiocu(void)
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{
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if (!mips_cm_present())
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return 0;
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return (read_gcr_config() & CM_GCR_CONFIG_NUMIOCU)
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>> __ffs(CM_GCR_CONFIG_NUMIOCU);
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}
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/**
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/**
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* mips_cm_l2sync - perform an L2-only sync operation
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* mips_cm_l2sync - perform an L2-only sync operation
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*
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*
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@ -108,4 +108,132 @@ static inline void clear_##unit##_##name(uint##sz##_t val) \
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#include <asm/mips-cm.h>
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#include <asm/mips-cm.h>
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#include <asm/mips-cpc.h>
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#include <asm/mips-cpc.h>
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/**
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* mips_cps_numclusters - return the number of clusters present in the system
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*
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* Returns the number of clusters in the system.
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*/
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static inline unsigned int mips_cps_numclusters(void)
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{
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unsigned int num_clusters;
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if (mips_cm_revision() < CM_REV_CM3_5)
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return 1;
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num_clusters = read_gcr_config() & CM_GCR_CONFIG_NUM_CLUSTERS;
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num_clusters >>= __ffs(CM_GCR_CONFIG_NUM_CLUSTERS);
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return num_clusters;
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}
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/**
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* mips_cps_cluster_config - return (GCR|CPC)_CONFIG from a cluster
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* @cluster: the ID of the cluster whose config we want
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*
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* Read the value of GCR_CONFIG (or its CPC_CONFIG mirror) from a @cluster.
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*
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* Returns the value of GCR_CONFIG.
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*/
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static inline uint64_t mips_cps_cluster_config(unsigned int cluster)
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{
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uint64_t config;
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if (mips_cm_revision() < CM_REV_CM3_5) {
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/*
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* Prior to CM 3.5 we don't have the notion of multiple
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* clusters so we can trivially read the GCR_CONFIG register
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* within this cluster.
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*/
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WARN_ON(cluster != 0);
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config = read_gcr_config();
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} else {
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/*
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* From CM 3.5 onwards we read the CPC_CONFIG mirror of
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* GCR_CONFIG via the redirect region, since the CPC is always
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* powered up allowing us not to need to power up the CM.
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*/
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mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL);
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config = read_cpc_redir_config();
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mips_cm_unlock_other();
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}
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return config;
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}
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/**
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* mips_cps_numcores - return the number of cores present in a cluster
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* @cluster: the ID of the cluster whose core count we want
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*
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* Returns the value of the PCORES field of the GCR_CONFIG register plus 1, or
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* zero if no Coherence Manager is present.
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*/
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static inline unsigned int mips_cps_numcores(unsigned int cluster)
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{
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if (!mips_cm_present())
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return 0;
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/* Add one before masking to handle 0xff indicating no cores */
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return (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES;
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}
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/**
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* mips_cps_numiocu - return the number of IOCUs present in a cluster
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* @cluster: the ID of the cluster whose IOCU count we want
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*
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* Returns the value of the NUMIOCU field of the GCR_CONFIG register, or zero
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* if no Coherence Manager is present.
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*/
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static inline unsigned int mips_cps_numiocu(unsigned int cluster)
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{
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unsigned int num_iocu;
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if (!mips_cm_present())
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return 0;
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num_iocu = mips_cps_cluster_config(cluster) & CM_GCR_CONFIG_NUMIOCU;
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num_iocu >>= __ffs(CM_GCR_CONFIG_NUMIOCU);
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return num_iocu;
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}
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/**
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* mips_cps_numvps - return the number of VPs (threads) supported by a core
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* @cluster: the ID of the cluster containing the core we want to examine
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* @core: the ID of the core whose VP count we want
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*
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* Returns the number of Virtual Processors (VPs, ie. hardware threads) that
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* are supported by the given @core in the given @cluster. If the core or the
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* kernel do not support hardware mutlti-threading this returns 1.
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*/
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static inline unsigned int mips_cps_numvps(unsigned int cluster, unsigned int core)
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{
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unsigned int cfg;
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if (!mips_cm_present())
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return 1;
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if ((!IS_ENABLED(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
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&& (!IS_ENABLED(CONFIG_CPU_MIPSR6) || !cpu_has_vp))
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return 1;
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mips_cm_lock_other(cluster, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
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if (mips_cm_revision() < CM_REV_CM3_5) {
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/*
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* Prior to CM 3.5 we can only have one cluster & don't have
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* CPC_Cx_CONFIG, so we read GCR_Cx_CONFIG.
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*/
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cfg = read_gcr_co_config();
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} else {
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/*
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* From CM 3.5 onwards we read CPC_Cx_CONFIG because the CPC is
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* always powered, which allows us to not worry about powering
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* up the cluster's CM here.
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*/
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cfg = read_cpc_co_config();
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}
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mips_cm_unlock_other();
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return (cfg + 1) & CM_GCR_Cx_CONFIG_PVPE;
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}
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#endif /* __MIPS_ASM_MIPS_CPS_H__ */
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#endif /* __MIPS_ASM_MIPS_CPS_H__ */
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@ -42,19 +42,10 @@ early_param("nothreads", setup_nothreads);
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static unsigned core_vpe_count(unsigned core)
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static unsigned core_vpe_count(unsigned core)
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{
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{
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unsigned cfg;
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if (threads_disabled)
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if (threads_disabled)
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return 1;
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return 1;
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if ((!IS_ENABLED(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
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return mips_cps_numvps(0, core);
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&& (!IS_ENABLED(CONFIG_CPU_MIPSR6) || !cpu_has_vp))
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return 1;
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mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
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cfg = read_gcr_co_config() & CM_GCR_Cx_CONFIG_PVPE;
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mips_cm_unlock_other();
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return cfg + 1;
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}
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}
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static void __init cps_smp_setup(void)
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static void __init cps_smp_setup(void)
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@ -64,7 +55,7 @@ static void __init cps_smp_setup(void)
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int c, v;
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int c, v;
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/* Detect & record VPE topology */
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/* Detect & record VPE topology */
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ncores = mips_cm_numcores();
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ncores = mips_cps_numcores(0);
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pr_info("%s topology ", cpu_has_mips_r6 ? "VP" : "VPE");
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pr_info("%s topology ", cpu_has_mips_r6 ? "VP" : "VPE");
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for (c = nvpes = 0; c < ncores; c++) {
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for (c = nvpes = 0; c < ncores; c++) {
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core_vpes = core_vpe_count(c);
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core_vpes = core_vpe_count(c);
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@ -138,7 +129,7 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
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}
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}
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/* Warn the user if the CCA prevents multi-core */
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/* Warn the user if the CCA prevents multi-core */
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ncores = mips_cm_numcores();
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ncores = mips_cps_numcores(0);
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if ((cca_unsuitable || cpu_has_dc_aliases) && ncores > 1) {
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if ((cca_unsuitable || cpu_has_dc_aliases) && ncores > 1) {
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pr_warn("Using only one core due to %s%s%s\n",
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pr_warn("Using only one core due to %s%s%s\n",
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cca_unsuitable ? "unsuitable CCA" : "",
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cca_unsuitable ? "unsuitable CCA" : "",
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@ -128,7 +128,7 @@ static int __init plat_enable_iocoherency(void)
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BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
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BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
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pr_info("Enabled Bonito IOBC coherency\n");
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pr_info("Enabled Bonito IOBC coherency\n");
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}
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}
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} else if (mips_cm_numiocu() != 0) {
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} else if (mips_cps_numiocu(0) != 0) {
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/* Nothing special needs to be done to enable coherency */
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/* Nothing special needs to be done to enable coherency */
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pr_info("CMP IOCU detected\n");
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pr_info("CMP IOCU detected\n");
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cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0));
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cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0));
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@ -201,7 +201,7 @@ void __init mips_pcibios_init(void)
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msc_mem_resource.start = start & mask;
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msc_mem_resource.start = start & mask;
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msc_mem_resource.end = (start & mask) | ~mask;
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msc_mem_resource.end = (start & mask) | ~mask;
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msc_controller.mem_offset = (start & mask) - (map & mask);
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msc_controller.mem_offset = (start & mask) - (map & mask);
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if (mips_cm_numiocu()) {
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if (mips_cps_numiocu(0)) {
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write_gcr_reg0_base(start);
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write_gcr_reg0_base(start);
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write_gcr_reg0_mask(mask |
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write_gcr_reg0_mask(mask |
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CM_GCR_REGn_MASK_CMTGT_IOCU0);
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CM_GCR_REGn_MASK_CMTGT_IOCU0);
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@ -213,7 +213,7 @@ void __init mips_pcibios_init(void)
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msc_io_resource.end = (map & mask) | ~mask;
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msc_io_resource.end = (map & mask) | ~mask;
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msc_controller.io_offset = 0;
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msc_controller.io_offset = 0;
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ioport_resource.end = ~mask;
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ioport_resource.end = ~mask;
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if (mips_cm_numiocu()) {
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if (mips_cps_numiocu(0)) {
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write_gcr_reg1_base(start);
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write_gcr_reg1_base(start);
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write_gcr_reg1_mask(mask |
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write_gcr_reg1_mask(mask |
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CM_GCR_REGn_MASK_CMTGT_IOCU0);
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CM_GCR_REGn_MASK_CMTGT_IOCU0);
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@ -198,7 +198,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
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mips_cm_probe();
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mips_cm_probe();
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mips_cpc_probe();
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mips_cpc_probe();
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if (mips_cm_numiocu()) {
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if (mips_cps_numiocu(0)) {
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/*
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/*
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* mips_cm_probe() wipes out bootloader
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* mips_cm_probe() wipes out bootloader
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* config for CM regions and we have to configure them
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* config for CM regions and we have to configure them
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